SLVUDA9 October   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 I/O Information
    2. 2.2 Jumper Information
    3. 2.3 Equipment
    4. 2.4 Hardware Setup
  9. 3Software
    1. 3.1 Software Setup
    2. 3.2 Test Procedure
      1. 3.2.1 Initial Power Up
      2. 3.2.2 I2C Register Communication Verification
      3. 3.2.3 Forward/Charge/Sink Mode Verification
      4. 3.2.4 Reverse/OTG/Source Mode Verification
      5. 3.2.5 Helpful Tips
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
      1. 4.2.1 PCB Layout Guidelines
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1.     Trademarks
  12. 6Revision History

3.2.2 I2C Register Communication Verification

Use the following steps for communication verification :

  1. In the EVM software, click the BQ25692EVM, BQ25692-Q1EVM button
    • Verify that the GUI reads BQ25692EVM, BQ25692-Q1EVM in the top right corner.
      Note:

      If the device reads BQ25692EVM, BQ25692-Q1EVM verify Section 2.4 and Section 3.2.1 steps have been followed.

  2. In the Field View (see Figure 3-2), make the following changes as necessary:
    • On the 8-bit tab:

      • In the Chip Multi-bit section, Set Watchdog to Disable

      • In the Chip Single-bit section, Set EN_CHG is not already (note that /CE bit overrides EN_CHG bit).

      • If a HIGHER cell count, regulation voltage, minimum system voltage and/or pre/charge/termination current is desired than set by the CELLS, VCHG and/or ICHG resistors, click the appropriate OVERRIDE bit in the Forward Single-bit section. The CELLS_PIN register is in the Forward Multi-bit section. The VREG and ICHG register are on the 16 Bit tab.

    • On the 16-bit tab
      • Set IINDPM to desired input current limit <= PS#1 match output current. Note that the actual input current limit is the lower the IINDPM register or ILIM_HIZ resistor clamp unless the EN_EXTILIM bit in the Forward Single-bit section of the 8 Bit tab is set to 0.

      • Set the VREG and/or ICHG registers to the desired setting.