SLVUDF6 September   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 System Description
      1. 1.3.1 Key System Specifications
      2. 1.3.2 End Equipment
      3. 1.3.3 Electricity Meter
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 System Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 Design Considerations
        1. 2.1.2.1 Voltage Measurement - Analog Front End
        2. 2.1.2.2 Current Measurement - Analog Front End
        3. 2.1.2.3 Input Voltage
  9. 3Software
    1. 3.1 Metrology Overview
      1. 3.1.1 Metrology Formulas
      2. 3.1.2 UART for PC GUI Communication
      3. 3.1.3 Direct Memory Access (DMA)
      4. 3.1.4 ADC Setup
      5. 3.1.5 Foreground Process
      6. 3.1.6 Background Process
      7. 3.1.7 Software Function per_sample_dsp ()
      8. 3.1.8 Frequency Measurement and Cycle Tracking
      9. 3.1.9 LED Pulse Generation
  10. 4Implementation Results
    1. 4.1 Evaluation Procedure
      1. 4.1.1 Equipment Setup
      2. 4.1.2 Test Procedure
        1. 4.1.2.1 Working with the Metrology GUI
        2. 4.1.2.2 Calibration
          1. 4.1.2.2.1 Voltage and Current Offset Calibration
          2. 4.1.2.2.2 Voltage and Current Gain Calibration
          3. 4.1.2.2.3 Active Power Gain Calibration
          4. 4.1.2.2.4 Offset Calibration
          5. 4.1.2.2.5 Phase Calibration
    2. 4.2 Performance Data and Results
      1. 4.2.1 Electricity Meter Metrology Accuracy Results
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Compliance Information
    1. 7.1 Compliance and Certifications
  14. 8Related Documentation

3.1.6 Background Process

Figure 3-3 shows the different events that occur when sampling voltage and current, where the items in green are done by the MSPM0G1106 hardware modules.

AMC-ADC-1PH-EVM Voltage and Current Sampling Events Figure 3-3 Voltage and Current Sampling Events

New current samples for each phase are ready every OSR, or 1024 modulation clock cycles for this design, thus resulting in 4000 samples per second over the SPI bus to MSPM0+ MCU. Once new samples are ready, the DRDY pin causes a GPIO interrupt on the MSPM0+ MCU, which triggers the Port ISR, and the background process is run within the Port ISR.

Figure 3-4 shows the background process, which mainly deals with timing-critical events in the test software.

AMC-ADC-1PH-EVM Background Process Figure 3-4 Background Process