SLVUDW7 May   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 Jumper Information
    5. 2.5 Test Points
  9. 3Software
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1.     Trademarks
  12. 6Related Documentation

2.1 Power Requirements

The AFE88XH1-FELC-EVM is loop-powered through the J2 terminal. The power source must provide from 8V to 30V across the LOOP+ and LOOP- connections, with a current capability of at least 50mA.

The loop power feeds two LDOs (3.3V and 1.8V) and a voltage reference (1.25V) which can power both the AFE88XH1-FELC-EVM and SNSR-DUAL-ADC-EVM. The loop power is also used for the OPA391 transimpedance amplifier which controls the loop current using an NPN bipolar junction transistor.

The AFE881H1 supports both 3.3V and 1.8V input to PVDD while the AFE882H1 only supports 3.3V input to PVDD. For detailed jumper information about the power input setup, see Section 2.4.

SPI or UART communication to the AFE88XH1 comes from the SNSR-DUAL-ADC-EVM, which interfaces with the host computer through a USB A-to-Micro-B cable connection.