SLVUDW7 May   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Header Information
    4. 2.4 Jumper Information
    5. 2.5 Test Points
  9. 3Software
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1.     Trademarks
  12. 6Related Documentation

2.3 Header Information

The AFE88XH1-FELC-EVM has one header: J1. The J1 header connects to the SNSR-DUAL-ADC-EVM board for communication and power transfer between the AFE88XH1 and MCU. For a description of the pins, see Table 2-1.

Table 2-1 J1 Header Description
Pin Number Description
1 GND
2 3.3V LDO output connection for VDD supply voltage
3 External VREF output connection from J3
4 1.8V LDO output connection for VDD supply voltage
5 MCU signal input to control shift register at power up
6 SCLK (SPI clock)
7 Not Used
8 SDI (SPI serial data input)
9 Not Used
10 SDO (SPI serial data output)
11 ALARM output from AFE88XH1
12 CS (SPI chip select)
13 Carrier Detect input
14 HART signal transmission output from AFE88XH1
15 AFE88XH1 Request to send input
16 HART signal receiver input to AFE88XH1