SNAA377 December   2025 LMK05318 , LMK05318B , LMK5B12204 , LMK5B12212 , LMK5B33216 , LMK5B33414 , LMK5C22212A , LMK5C23208A , LMK5C33216 , LMK5C33216A , LMK5C33414A

 

  1.   1
  2.   Trademarks
  3.   Abstract
  4. 1Introduction
  5. 2General Termination Guidelines
    1. 2.1 Identify the Driver and Receiver Requirements
    2. 2.2 Determine the Coupling Type
      1. 2.2.1 DC-Coupled Signal
      2. 2.2.2 AC-Coupled Signal
  6. 3Differential
    1. 3.1 Setting the Common-Mode Voltage (Thevenin Termination)
    2. 3.2 LVPECL
      1. 3.2.1 DC-Coupled LVPECL
      2. 3.2.2 AC-Coupled LVPECL
    3. 3.3 LVDS
      1. 3.3.1 DC-Coupled LVDS
      2. 3.3.2 AC-Coupled LVDS
    4. 3.4 HSDS
      1. 3.4.1 DC-Coupled HSDS
      2. 3.4.2 AC-Coupled HSDS
    5. 3.5 HCSL
      1. 3.5.1 DC-Coupled HCSL
      2. 3.5.2 AC-Coupled HCSL
    6. 3.6 LP-HCSL
      1. 3.6.1 DC-Coupled LP-HCSL
      2. 3.6.2 AC-Coupled LP-HCSL
  7. 4Single-Ended
    1. 4.1 LVCMOS
      1. 4.1.1 DC-Coupled LVCMOS (Series Termination)
      2. 4.1.2 AC-Coupled LVCMOS (Series Termination)
    2. 4.2 Differential P or N
      1. 4.2.1 DC-Coupled Differential P or N
  8. 5Summary
  9. 6References

Abstract

Output signals must be terminated to generate a toggling voltage signal that has a particular voltage swing and DC bias. When properly terminated, the transmission line (trace) impedance is maintained. Impedance matching is necessary to prevent reflections, overshoot, undershoot, and ringing at the outputs. Care must be taken with the PCB layout design as the trace width, trace gap, and stack-up all contribute to the trace impedance. This application note describes the general guidelines and steps required to terminate differential and single-ended signals. Layout techiniques are not covered in this application note.