Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW
Product details
Parameters
Package | Pins | Size
Features
- BAW APLL with 40 fs RMS jitter at 491.52 MHz
- Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
- Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
- -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
- Two differential or single-ended DPLL inputs
- 1 Hz to 800 MHz differential
- Hitless switching with phase cancellation and/or phase slew control
- Priority based reference selection
- 16 outputs with programmable format
- 1000 MHz LVPECL/LVDS/HSDS
- 3000 MHz CML on OUT4 and OUT6
- 200 MHz LVCMOS on OUT0 and OUT1
- Single 3.3-V supply with internal LDOs
- I2C or 3-wire/4-wire SPI interface
- Requires single XO/TCXO/OCXO
- 40-bit DPLL or APLL DCO, < 1 ppt
- Holdover with phase build out upon exit
- Zero delay mode with programmable delay
- User programmable EEPROM
- Supports 105 °C PCB temperature
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Description
The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.
The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.
The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TIs proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.
The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LMK5C33216 Ultra-Low Jitter Clock Synchronizer with JESD204B for Wireless Communications with BAW datasheet (Rev. B) | Mar. 10, 2021 |
User guide | LMK5C33216EVM User's Guide (Rev. A) | Feb. 15, 2021 | |
Application note | ITU-T G.8262 Compliance Test Results for the LMK5C33216 | Dec. 23, 2020 | |
User guide | LMK5C33216 Programming Guide | Dec. 18, 2020 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Three Digital PLL (DPLL) with programmable bandwidths and three fractional analog PLLs (APLLs) for flexible clock generation
- Two reference inputs to the DPLL supporting hitless switching & holdover
- 16 output clocks. Outputs driven by BAW are capable of sub 50-fs RMS phase jitter (12 kHz to 20 MHz)
- (...)
Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
- Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
- Presents clear and intuitive block (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RGC) | 64 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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