Product details

Function Clock network synchronizer, Ultra-low jitter clock generator Number of outputs 4 RMS jitter (fs) 50 Output frequency (Min) (MHz) 0.000001 Output frequency (Max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Output type LVDS, CML, LVPECL, HCSL, LVCMOS Supply voltage (Min) (V) 3.135 Supply voltage (Max) (V) 3.465 Features Integrated EEPROM, I2C, SPI, Pin programmable Operating temperature range (C) -40 to 85
Function Clock network synchronizer, Ultra-low jitter clock generator Number of outputs 4 RMS jitter (fs) 50 Output frequency (Min) (MHz) 0.000001 Output frequency (Max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Output type LVDS, CML, LVPECL, HCSL, LVCMOS Supply voltage (Min) (V) 3.135 Supply voltage (Max) (V) 3.465 Features Integrated EEPROM, I2C, SPI, Pin programmable Operating temperature range (C) -40 to 85
VQFN (RGZ) 48 49 mm² 7 x 7
  • One Digital Phase-Locked Loop (DPLL) With:
    • Hitless Switching: ±50-ps Phase Transient
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
    • 50-fs RMS Jitter at 312.5 MHz (APLL1)
    • 125-fs RMS Jitter at 155.52 MHz (APLL2)
  • Two Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Four Clock Outputs with Programmable Drivers
    • Up to Four Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
  • EEPROM / ROM for Custom Clocks on Power-Up
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 800 MHz on Input
    • XO/TCXO/OCXO Input: 10 to 100 MHz
    • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
    • Advanced Clock Monitoring and Status
    • I2C or SPI Interface
  • PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40 °C to +85 °C
  • One Digital Phase-Locked Loop (DPLL) With:
    • Hitless Switching: ±50-ps Phase Transient
    • Programmable Loop Bandwidth With Fastlock
    • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
  • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
    • 50-fs RMS Jitter at 312.5 MHz (APLL1)
    • 125-fs RMS Jitter at 155.52 MHz (APLL2)
  • Two Reference Clock Inputs
    • Priority-Based Input Selection
    • Digital Holdover on Loss of Reference
  • Four Clock Outputs with Programmable Drivers
    • Up to Four Different Output Frequencies
    • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
  • EEPROM / ROM for Custom Clocks on Power-Up
  • Flexible Configuration Options
    • 1 Hz (1 PPS) to 800 MHz on Input
    • XO/TCXO/OCXO Input: 10 to 100 MHz
    • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
    • Advanced Clock Monitoring and Status
    • I2C or SPI Interface
  • PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
  • 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
  • Industrial Temperature Range: –40 °C to +85 °C

The LMK5B12204 is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The LMK5B12204 is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 7
Type Title Date
* Data sheet LMK5B12204 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domain datasheet (Rev. A) 05 Jan 2021
User guide LMK5B12204 register programming manual 01 Jun 2020
Application note ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) 22 Feb 2019
Application note Supported synchronization modes for TI network synchronizers (Rev. A) 22 Feb 2019
Application note Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) 22 Feb 2019
White paper TI BAW technology enables ultra-low jitter clocks for high-speed networks 17 Feb 2019
Application note How to use the LMK05318 as a jitter cleaner 16 Jan 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK05318BEVM — Network synchronizer clock evaluation module

To get started with this evaluation module:
Step 1: Buy the EVM
Step 2: Setup the default jumpers as shown in the user's guide
Step 3: Download TICS Pro and follow the EVM quick start instructions

This is an evaluation module (EVM) for the LMK05318B network synchronizer clock device.
The EVM can be used (...)
In stock
Limit: 2
Support software

TICS Pro Software v1.7.2 (Rev. AL)

SNAC072AL.ZIP (61999 KB)
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos