LMK5B12204

• One Digital Phase-Locked Loop (DPLL) With:
  • Hitless Switching: ±50-ps Phase Transient
  • Programmable Loop Bandwidth With Fastlock
  • Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
• Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter Performance:
  • 50-fs RMS Jitter at 312.5 MHz (APLL1)
  • 130-fs RMS Jitter at 155.52 MHz (APLL2)
• Two Reference Clock Inputs
  • Priority-Based Input Selection
  • Digital Holdover on Loss of Reference
• Four Clock Outputs with Programmable Drivers
  • Up to Four Different Output Frequencies
  • AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8-V LVCMOS Output Formats
• EEPROM / ROM for Custom Clocks on Power-Up
• Flexible Configuration Options
  • 1 Hz (1 PPS) to 800 MHz on Input
  • XO/TCXO/OCXO Input: 10 to 100 MHz
  • DCO Mode: < 0.001 ppb/Step for Precise Clock Steering (IEEE 1588 PTP Slave)
  • Advanced Clock Monitoring and Status
  • I²C or SPI Interface
• PSNR: –83 dBc (50-mVpp Noise on 3.3-V Supply)
• 3.3-V Supply With 1.8-V, 2.5-V, or 3.3-V Outputs
• Industrial Temperature Range: –40 °C to +85 °C

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The LMK5B12204 is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.

The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The DPLL supports programmable loop bandwidth for jitter and wander attenuation, while the two APLLs support fractional frequency translation for flexible clock generation. The synchronization options supported on the DPLL include hitless switching with phase cancellation, digital holdover, and DCO mode with less than 0.001-ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1-PPS (pulse-per-second) reference input. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.

The device can use a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronization standards. Otherwise, the device can use a standard XO when free-run or holdover frequency stability and wander are not critical. The device is fully programmable through I²C or SPI interface, and supports custom frequency configuration on power up with the internal EEPROM or ROM. The EEPROM is factory pre-programmed and can be programmed in-system, if needed.