4 CDC6C Clocking DP83822 Evaluation

Jitter and Bit Error Rate (BER) are two important measurements when using Ethernet PHY devices as this affects signal integrity and packet data. The worse the jitter the worse the timing accuracy of data signal. This results in Ethernet packer corruption. The following highlights test procedure, set up and results of both jitter and BER comparing on board quartz oscillator and TI CDC6C BAW based oscillator.

Test conducted using Ethernet PHY, DP83822 EVM, to compare with onboard quartz oscillator and BAW oscillator CDC6CE025000ADLFR. BAW oscillator output is coming from CDC6CEVM connected to Ethernet PHY EVM through jumper cable connected to the clock in pin. See Figure 4-1 illustrating location of jumper pins in red box.

Figure 4-1 DP83822 EVM

To test the oscillators jitter performance the PHY EVM is connected to a test fixture where channels A and B are read. MLT-3 Pattern on MDI CHA (P9) and CHB (P10) is generated in test mode. Figure 4-2 and Figure 4-3 show the jitter test set up and Table 4-1 highlights results of quartz v CDC6C oscillator effect on PHY output.

Figure 4-2 Jitter Test Block Diagram

Figure 4-3 Jitter Test Fixture

To test oscillator effect on BER the DP83822 PHY EVM is connected to a packet generator with 100m copper interface while looping back the packets into the PHY. BER tested using UNH interoperability test suite. This test maintained the same oscillator set up as jitter test, see Figure 4-4.

Data transmitted and received from the packet generator are random data pattern and random frame size through a continuous packet generation. 113,505,895,589 bytes are transmitted and received with no failures for 1e11 bytes observed as highlighted in Table 4-1 using CDC6C as the reference input clock to DP83822.

Figure 4-4 Bit Error Rate Test Block Diagram

Figure 4-5 BER Test Results of DP83822 Clocked With CDC6C Oscillator

Figure 4-6 Phase Noise and Jitter Measurement Comparing Quartz and BAW Oscillators