SNAS739E June   2018  – December 2025 LMX2615-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOCal”
        3. 6.3.6.3 Lock Detect Indicator Set as Type “Vtune and VCOCal”
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Buffer
      10. 6.3.10 Powerdown Modes
      11. 6.3.11 Treatment of Unused Pins
      12. 6.3.12 Phase Synchronization
        1. 6.3.12.1 General Concept
        2. 6.3.12.2 Categories of Applications for SYNC
        3. 6.3.12.3 Procedure for Using SYNC
        4. 6.3.12.4 SYNC Input Pin
      13. 6.3.13 Phase Adjust
      14. 6.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
      15. 6.3.15 SYSREF
      16. 6.3.16 Pin Modes
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
    6. 6.6 Register Maps
      1. 6.6.1 Register Map
        1. 6.6.1.1  R0 Register (Offset = 0x0) [reset = 0x241C]
        2. 6.6.1.2  R1 Register (Offset = 0x1) [reset = 0x80C]
        3. 6.6.1.3  R2 Register (Offset = 0x2) [reset = 0x500]
        4. 6.6.1.4  R3 Register (Offset = 0x3) [reset = 0x642]
        5. 6.6.1.5  R4 Register (Offset = 0x4) [reset = 0xE43]
        6. 6.6.1.6  R5 Register (Offset = 0x5) [reset = 0x3E8]
        7. 6.6.1.7  R6 Register (Offset = 0x6) [reset = 0x7802]
        8. 6.6.1.8  R7 Register (Offset = 0x7) [reset = 0xB2]
        9. 6.6.1.9  R8 Register (Offset = 0x8) [reset = 0x2000]
        10. 6.6.1.10 R9 Register (Offset = 0x9) [reset = 0x1604]
        11. 6.6.1.11 R10 Register (Offset = 0xA) [reset = 0x10D8]
        12. 6.6.1.12 R11 Register (Offset = 0xB) [reset = 0x18]
        13. 6.6.1.13 R12 Register (Offset = 0xC) [reset = 0x5001]
        14. 6.6.1.14 R13 Register (Offset = 0xD) [reset = 0x4000]
        15. 6.6.1.15 R14 Register (Offset = 0xE) [reset = 0x1E70]
        16. 6.6.1.16 R15 Register (Offset = 0xF) [reset = 0x64F]
        17. 6.6.1.17 R16 Register (Offset = 0x10) [reset = 0x80]
        18. 6.6.1.18 R17 Register (Offset = 0x11) [reset = 0x12C]
        19. 6.6.1.19 R18 Register (Offset = 0x12) [reset = 0x64]
        20. 6.6.1.20 R19 Register (Offset = 0x13) [reset = 0x27B7]
        21. 6.6.1.21 R20 Register (Offset = 0x14) [reset = 0xF848]
        22. 6.6.1.22 R21 Register (Offset = 0x15) [reset = 0x401]
        23. 6.6.1.23 R22 Register (Offset = 0x16) [reset = 0x1]
        24. 6.6.1.24 R23 Register (Offset = 0x17) [reset = 0x7C]
        25. 6.6.1.25 R24 Register (Offset = 0x18) [reset = 0x71A]
        26. 6.6.1.26 R25 Register (Offset = 0x19) [reset = 0x624]
        27. 6.6.1.27 R26 Register (Offset = 0x1A) [reset = 0xDB0]
        28. 6.6.1.28 R27 Register (Offset = 0x1B) [reset = 0x2]
        29. 6.6.1.29 R28 Register (Offset = 0x1C) [reset = 0x488]
        30. 6.6.1.30 R29 Register (Offset = 0x1D) [reset = 0x318C]
        31. 6.6.1.31 R30 Register (Offset = 0x1E) [reset = 0x318C]
        32. 6.6.1.32 R31 Register (Offset = 0x1F) [reset = 0x43EC]
        33. 6.6.1.33 R32 Register (Offset = 0x20) [reset = 0x393]
        34. 6.6.1.34 R33 Register (Offset = 0x21) [reset = 0x1E21]
        35. 6.6.1.35 R34 Register (Offset = 0x22) [reset = 0x0]
        36. 6.6.1.36 R35 Register (Offset = 0x23) [reset = 0x4]
        37. 6.6.1.37 R36 Register (Offset = 0x24) [reset = 0x46]
        38. 6.6.1.38 R37 Register (Offset = 0x25) [reset = 0x404]
        39. 6.6.1.39 R38 Register (Offset = 0x26) [reset = 0xFD51]
        40. 6.6.1.40 R39 Register (Offset = 0x27) [reset = 0xDA80]
        41. 6.6.1.41 R40 Register (Offset = 0x28) [reset = 0x0]
        42. 6.6.1.42 R41 Register (Offset = 0x29) [reset = 0x0]
        43. 6.6.1.43 R42 Register (Offset = 0x2A) [reset = 0x0]
        44. 6.6.1.44 R43 Register (Offset = 0x2B) [reset = 0x0]
        45. 6.6.1.45 R44 Register (Offset = 0x2C) [reset = 0x1FA3]
        46. 6.6.1.46 R45 Register (Offset = 0x2D) [reset = 0xC8DF]
        47. 6.6.1.47 R46 Register (Offset = 0x2E) [reset = 0x7FD]
        48. 6.6.1.48 R47 Register (Offset = 0x2F) [reset = 0x300]
        49. 6.6.1.49 R48 Register (Offset = 0x30) [reset = 0x300]
        50. 6.6.1.50 R49 Register (Offset = 0x31) [reset = 0x4180]
        51. 6.6.1.51 R50 Register (Offset = 0x32) [reset = 0x0]
        52. 6.6.1.52 R51 Register (Offset = 0x33) [reset = 0x80]
        53. 6.6.1.53 R52 Register (Offset = 0x34) [reset = 0x420]
        54. 6.6.1.54 R53 Register (Offset = 0x35) [reset = 0x0]
        55. 6.6.1.55 R54 Register (Offset = 0x36) [reset = 0x0]
        56. 6.6.1.56 R55 Register (Offset = 0x37) [reset = 0x0]
        57. 6.6.1.57 R56 Register (Offset = 0x38) [reset = 0x0]
        58. 6.6.1.58 R57 Register (Offset = 0x39) [reset = 0x20]
        59. 6.6.1.59 R58 Register (Offset = 0x3A) [reset = 0x8001]
        60. 6.6.1.60 R59 Register (Offset = 0x3B) [reset = 0x1]
        61. 6.6.1.61 R60 Register (Offset = 0x3C) [reset = 0x9C4]
        62. 6.6.1.62 R61 Register (Offset = 0x3D) [reset = 0xA8]
        63. 6.6.1.63 R62 Register (Offset = 0x3E) [reset = 0x322]
        64. 6.6.1.64 R63 Register (Offset = 0x3F) [reset = 0x0]
        65. 6.6.1.65 R64 Register (Offset = 0x40) [reset = 0x1388]
        66. 6.6.1.66 R65 Register (Offset = 0x41) [reset = 0x0]
        67. 6.6.1.67 R66 Register (Offset = 0x42) [reset = 0x1F4]
        68. 6.6.1.68 R67 Register (Offset = 0x43) [reset = 0x0]
        69. 6.6.1.69 R68 Register (Offset = 0x44) [reset = 0x3E8]
        70. 6.6.1.70 R69 Register (Offset = 0x45) [reset = 0x0]
        71. 6.6.1.71 R70 Register (Offset = 0x46) [reset = 0xC350]
        72. 6.6.1.72 R71 Register (Offset = 0x47) [reset = 0x80]
        73. 6.6.1.73 R72 Register (Offset = 0x48) [reset = 0x1]
        74. 6.6.1.74 R73 Register (Offset = 0x49) [reset = 0x3F]
        75. 6.6.1.75 R74 Register (Offset = 0x4A) [reset = 0x0]
        76. 6.6.1.76 R75 Register (Offset = 0x4B) [reset = 0x800]
        77. 6.6.1.77 R76 Register (Offset = 0x4C) [reset = 0xC]
        78. 6.6.1.78 R77 Register (Offset = 0x4D) [reset = 0x0]
        79. 6.6.1.79 R78 Register (Offset = 0x4E) [reset = 0x64]
        80. 6.6.1.80 R79 - R104 Register (Offset = 0x4F - 0x68) [reset = 0x0]
        81. 6.6.1.81 R105 Register (Offset = 0x69) [reset = 0x4440]
        82. 6.6.1.82 R106 Register (Offset = 0x6A) [reset = 0x7]
        83. 6.6.1.83 R107 - R109 Register (Offset = 0x6B - 0x6D) [Read only]
        84. 6.6.1.84 R110 Register (Offset = 0x6E) [Read only]
        85. 6.6.1.85 R111 Register (Offset = 0x6F) [Read only]
        86. 6.6.1.86 R112 Register (Offset = 0x70) [Read only]
        87. 6.6.1.87 R113 Register (Offset = 0x71) [Read only]
        88. 6.6.1.88 R114 Register (Offset = 0x72) [reset = 0x26F]
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer Pullup
        1. 7.1.4.1 Resistor Pullup
        2. 7.1.4.2 Inductor Pullup
        3. 7.1.4.3 Combination Pullup
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-Ended Termination of Unused Output
        2. 7.1.5.2 Differential Termination
    2. 7.2 External Loop Filter
    3. 7.3 Typical Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
      3. 7.3.3 Application Curve
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
      3. 7.5.3 Footprint Example on PCB Layout
      4. 7.5.4 Radiation Environments
        1. 7.5.4.1 Total Ionizing Dose
        2. 7.5.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples

5.7 Timing Diagrams

LMX2615-SP Trigger Signals Timing Diagram Figure 5-1 Trigger Signals Timing Diagram
LMX2615-SP SPI Timing Diagram Figure 5-2 SPI Timing Diagram

LMX2615-SP supports SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=01 CPHA=1).

To write registers:

  • The R/W bit must be set to 0.
  • The data on SDI pin is clocked into the shift register upon the rising edge of the clocks on SCK pin. On the rising edge of the 24th clock cycle, the data is transferred from the data field into the selected register bank.
  • The CSB pin can be held high after programming, which causes the LMX2615-SP to ignore clock pulses.
  • If the SCK and SDI lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared between devices, the phase noise can be degraded during the time of this programming.

To read back registers:

  • The R/W bit must be set to 1.
  • The data field contents on the SDI line are ignored.
  • The read back data on MUXout pin is clocked out starting from the falling edge of the 8th clock cycle.
  • MUXout pin is tri-state only if MUXOUT_CTRL = 0.