Product details

Integrated VCO Yes Output frequency (min) (MHz) 40 Output frequency (max) (MHz) 15000 Normalized PLL phase noise (dBc/Hz) -236 Current consumption (mA) 360 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Rating Space Operating temperature range (°C) -55 to 125 Lock time (µs) (typ) Loop BW dependent
Integrated VCO Yes Output frequency (min) (MHz) 40 Output frequency (max) (MHz) 15000 Normalized PLL phase noise (dBc/Hz) -236 Current consumption (mA) 360 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Rating Space Operating temperature range (°C) -55 to 125 Lock time (µs) (typ) Loop BW dependent
CFP (HBD) 64 400 mm² 20 x 20
  • Radiation specifications:
    • Single event latch-up >120 MeV-cm2/mg
    • Total ionizing dose to 100 krad(Si)
    • SMD 5962R1723601VXC
  • 40-MHz to 15.2-GHz output frequency
  • –110-dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45 fs RMS jitter at 8 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • Up to 200-MHz phase detector frequency
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • 3.3-V single power supply operation
  • 71 pre-selected pin modes
  • 11 × 11 mm² 64-lead CQFP ceramic package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool
  • Radiation specifications:
    • Single event latch-up >120 MeV-cm2/mg
    • Total ionizing dose to 100 krad(Si)
    • SMD 5962R1723601VXC
  • 40-MHz to 15.2-GHz output frequency
  • –110-dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
  • 45 fs RMS jitter at 8 GHz (100 Hz to 100 MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –129 dBc/Hz
    • Up to 200-MHz phase detector frequency
  • Synchronization of output phase across multiple devices
  • Support for SYSREF with 9-ps resolution programmable delay
  • 3.3-V single power supply operation
  • 71 pre-selected pin modes
  • 11 × 11 mm² 64-lead CQFP ceramic package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool

The LMX2615-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 40 MHz and 15.2 GHz without a doubler, which eliminates the need for ½ harmonic filters. The VCO on this device covers an entire octave so the frequency coverage is complete down to 40 MHz. The high performance PLL with a figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2615-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in any use case including the one with fractional engine or output divider enabled. It also adds support for either generating or repeating SYSREF (compliant to JESD204B standard), making it an ideal low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead CQFP ceramic package.

The LMX2615-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 40 MHz and 15.2 GHz without a doubler, which eliminates the need for ½ harmonic filters. The VCO on this device covers an entire octave so the frequency coverage is complete down to 40 MHz. The high performance PLL with a figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2615-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in any use case including the one with fractional engine or output divider enabled. It also adds support for either generating or repeating SYSREF (compliant to JESD204B standard), making it an ideal low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead CQFP ceramic package.

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Design & development

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Evaluation board

LMX2615EVM-CVAL — Space grade synthesizer evaluation module

The LMX2615EVM-CVAL evaluation module (EVM) is designed for evaluating the LMX2615-SP product. It includes the assembled PCB and uses Reference Pro to program the board and also provide a 100-MHz input reference. The board is assembled with the LMX2615W-MPR engineering sample and can be used to (...)
User guide: PDF | HTML
Not available on TI.com
Simulation model

LMX2615 IBIS Model

SNAM229.ZIP (45 KB) - IBIS Model
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Reference designs

TIDA-010191 — Space-grade multichannel JESD204B 15-GHz clocking reference design

Phased-array antennas and digital beamforming are key technologies that will boost the performance of future spaceborne radar imaging and broadband satellite communication systems. Digital beamforming, unlike analog beamforming, typically requires a set of data converters per antenna element. (...)
Design guide: PDF
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CFP (HBD) 64 View options

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