SNAS833B November   2021  – August 2025 CDCDB400

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fail-Safe Input
      2. 7.3.2 Output Enable Control
      3. 7.3.3 SMBus
        1. 7.3.3.1 SMBus Address Assignment
    4. 7.4 Device Functional Modes
      1. 7.4.1 CKPWRGD_PD# Function
      2. 7.4.2 OE[3:0]# and SMBus Output Enables
      3. 7.4.3 Output Slew Rate Control
      4. 7.4.4 Output Impedance Control
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 CDCDB400 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Enable Control Method
        2. 9.2.2.2 SMBus Address
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TICS Pro
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.3.1 SMBus Address Assignment

The SMBus address is assigned by configuring the SADR0 pin which is capable of supporting three levels. This configuration allows the CDCDB400 to assume three different SMBus addresses.

The SMBus address pin is sampled when PWRGD is set to 1. See Table 7-1 for address pin configuration. The address can only be changed by power cycling the device.

Table 7-1 SMBus Address Assignment
SADR0 SMBus ADDRESS : WRITE OPERATION (READ/WRITE=0) SMBus ADDRESS : READ OPERATION (READ/WRITE=1)
L 0xD8 0xD9
M 0xDA 0xDB
H 0xDE 0xDF