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CDCDB400

ACTIVE

4-output clock buffer for PCIe® Gen 1 to Gen 7

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Data sheet

CDCDB400

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 38 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
Number of outputs 4 Additive RMS jitter (typ) (fs) 38 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 105 Rating Catalog Output type LP-HCSL Input type LP-HCSL
VQFN (RHB) 32 25 mm² 5 x 5
  • 4 LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output terminations
  • 4 hardware output enable (OE#) controls

  • Additive phase jitter after PCIE Gen 7 filter: 11.3fs, RMS (maximum)

  • Additive phase jitter after PCIE Gen 6 filter: 16.1fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50ps
  • Input-to-output delay: < 3ns

  • Fail-safe input

  • Programmable output slew rate control

  • 3 selectable SMBus addresses

  • 3.3V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 46mA maximum
  • 5mm × 5mm, 32-pin VQFN package
  • 4 LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output terminations
  • 4 hardware output enable (OE#) controls

  • Additive phase jitter after PCIE Gen 7 filter: 11.3fs, RMS (maximum)

  • Additive phase jitter after PCIE Gen 6 filter: 16.1fs, RMS (maximum)
  • Additive phase jitter after PCIE Gen 5 filter: 25fs, RMS (maximum)
  • Additive phase jitter after DB2000Q filter: 38fs, RMS (maximum)
  • Supports Common Clock (CC) and Individual Reference (IR) architectures
    • Spread spectrum-compatible
  • Output-to-output skew: < 50ps
  • Input-to-output delay: < 3ns

  • Fail-safe input

  • Programmable output slew rate control

  • 3 selectable SMBus addresses

  • 3.3V core and IO supply voltages
  • Hardware-controlled low power mode (PD#)
  • Current consumption: 46mA maximum
  • 5mm × 5mm, 32-pin VQFN package

The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-7, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5mm × 5mm, 32-pin VQFN package.

The CDCDB400 is a 4-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-7, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The SMBus interface and four output enable pins allow the configuration and control of all four outputs individually. The CDCDB400 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. The device also meets or exceeds the parameters in the DB2000Q specification. The CDCDB400 is packaged in a 5mm × 5mm, 32-pin VQFN package.
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* Data sheet CDCDB400 DB800ZL-Compliant 4-Output Clock Buffer for PCIe Gen 1 to Gen 7 datasheet (Rev. B) PDF | HTML 11 Aug 2025

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