SNAU252 June   2020 LMK04832-SP

 

  1.   LMK04832EVM-CVAL User’s Guide
    1.     Trademarks
    2. 1  Evaluation Board Kit Contents
    3. 2  Quick Start
      1. 2.1 Quick Start Description
        1. 2.1.1 Clock Outputs Page Description
        2. 2.1.2 TICS Pro Tips
    4. 3  PLL Loop Filters and Loop Parameters
      1. 3.1 PLL1 Loop Filter
      2. 3.2 PLL2 Loop Filter
    5. 4  Default TICS Pro Mode
    6. 5  Using TICS Pro to Program the LMK04832-SP
      1. 5.1 Start TICS Pro Application
      2. 5.2 Select Device
      3. 5.3 Program the Device
      4. 5.4 Restoring a Default Mode
      5. 5.5 Visual Confirmation of Frequency Lock
      6. 5.6 Enable Clock Outputs
    7. 6  Evaluation Board Inputs and Outputs
    8. 7  Recommended Test Equipment
    9. 8  Length Matching
    10. 9  Schematics
    11. 10 Bill of Materials
  2.   A TICS Pro Usage
    1.     A.1 Communication Setup
    2.     A.2 User Controls
    3.     A.3 Raw Registers Page
    4.     A.4 Set Modes Page
    5.     A.5 Holdover Page
    6.     A.6 CLKinX Control Page
    7.     A.7 PLL1 and 2 Page
    8.     A.8 SYNC / SYSREF Page
    9.     A.9 Clock Outputs Page
    10.     A.10 Other Page
    11.     A.11 Current Calculator Page
    12.     A.12 Burst Page

A.8 SYNC / SYSREF Page

The SYNC / SYSREF page allows some mode set buttons for JESD204B features. The SYNC dividers button will stop all SYNC inputs, set normal SYNC mode, enable all dividers for SYNC, issue a SYNC by toggling SYNC_POL, set all dividers to ignore SYNC, then return any other changed parameter to its original state. This is a nice feature to ensure all outputs are synchronized together or to be run after changing the digital delay value which requires a SYNC to update. This functionality is also available on any other page through the toolbar as SYNC Dividers.

NOTE

To use SYNC or SYSREF, ensure that SYNC_EN = 1. To use SYSREF in continuous, pulser, or reclocked modes, be sure SYSREF_PD = 0.

The SCLKX_Y_DIS_MODE bits allow the clock outputs to be disabled or set to a low state. Because values 1 and 2 are only conditionally set by the SYSREF_GBL_PD bit, it is possible to power up or power down several SYSREF outputs by programming only one register. When changing between 0x00 (Active) and (0x01) Conditional Low, keeping the SYSREF_CLR = 1 during transition will prevent glitch pulses from the SYSREF output.

SYNC-SYSREF_snau252.gifFigure 20. TICS Pro - SYNC / SYSREF Page