SNAU260A October 2020 – February 2021 LMK5C33216
ADVANCE INFORMATION
Cascading APLLs is controlled by the APLL source box, circled in Figure 6-12. This box is programmed bitwise and is automatically set when generating a frequency plan. The XO_OUT_BUF_EN register in the Input Control section of the User Controls tab is automatically set to enable or disable the XO Output Buffer. The PLLx_RDIV_XO_EN is automatically checked/unchecked in each APLLx tab depending on whether each APLL is using the XO input.