SNLA266A January   2016  – December 2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I

 

  1.   1
  2.   DP8382x IEEE 802.3u Compliance and Debug
  3.   Trademarks
  4. 1Terminology
  5. 2Standards and System Requirements
    1. 2.1 Standards
    2. 2.2 Test Equipment Suppliers
    3. 2.3 Test Equipment Requirements
  6. 3Ethernet Physical Layer Compliance Testing
    1. 3.1 Standard Test Setup and Procedures
    2. 3.2 100BASE-TX Compliance Testing
      1. 3.2.1 Template (Active Output Interface)
      2. 3.2.2 Differential Output Voltage
      3. 3.2.3 Rise and Fall Time
      4. 3.2.4 Waveform Overshoot
      5. 3.2.5 Jitter
      6. 3.2.6 Duty Cycle Distortion
      7. 3.2.7 Return Loss
    3. 3.3 10BASE-Te Compliance Testing
      1. 3.3.1 Link Pulse
      2. 3.3.2 10BASE-Te Standard
        1. 3.3.2.1 TP_IDL
        2. 3.3.2.2 MAU, Internal
        3. 3.3.2.3 Jitter With TPM
        4. 3.3.2.4 Jitter Without TPM
        5. 3.3.2.5 Differential Voltage
        6. 3.3.2.6 Common-Mode Voltage
        7. 3.3.2.7 Return Loss
        8. 3.3.2.8 Harmonic Content
  7. 4How to Tune DP83825 VoD Swing
    1. 4.1 Example of Tuning DP83825 VoD Swing
  8. 5IEEE802.3u Compliance Testing Scripts for the DP8382x
  9. 6References
  10. 7Revision History

4 How to Tune DP83825 VoD Swing

DP83825 has additional control to tune VoD swing. This control can be used to verify that the device is within compliance levels set by IEEE 802.3.The standard defines a ±5% variation of VoD. This parameter is heavily influenced by magnetics, connector, test fixture, layout, and all of the aforementioned listed tolerances.

Note: For best practices, layout guidelines in Ethernet PHY PCB Design Layout Checklist application note must be followed, and transformer specification requirements located in the DP83825I Low Power 10/100 Mbps Ethernet Physical Layer Transceiver data sheet must also be met, before register tuning.

To tune the PHY for the appropriate signal level, measuring the signal level is advised to understand how much (if applicable) the signal needs to be adjusted. Once measured, the following table can be used to determine the register configurations needed. Please note that this process needs to be redone for each individual unit. In addition, the following registers are classified as extended registers and must be written to as outlined in the DP83825I Low Power 10/100 Mbps Ethernet Physical Layer Transceiver data sheet.

Table 4-1 VoD Tuning Register Configurations
VoD Change0x30B0x30C0x30E
-12.5%0xC800xEOffset_0
-11.25%Offset_1
-10%Offset_2
-8.75%0xC400xFOffset_-2
-8%Offset_-1
-6.25%Offset_0
-5%Offset_1
-3.75%Offset_2
-2.5%0xC000x10Offset_-2
-1.25%Offset_-1
0% (Default)Offset_0
+1.25%Offset_1
+2.5%Offset_2
+3.75%0xBC00x11Offset_-2
+5%Offset_-1
+6.25%Offset_0
+7.5%Offset_1
+8.75%Offset_2
+10%0xB800x12Offset_-2
+11.25%Offset_-1
+12.5%Offset_0

To calculate Offset_X:

  1. Read Reg 0x333. Note this value varies between units
  2. A = 0x333[15:11] converted to decimal
  3. B = 0x333[10:6] converted to decimal
  4. C = 8 - A + B. This variable is bounded between 0 and 15. If C is calculated to be outside the bounds, the variable C must be rounded back to the nearest bound. If C is calculated to be -2, set C to equal 0
  5. D(x) = C + x, where x is determined using Reg 0x30E column in Table 4-1
  6. Offset_x = [ 2 D ( x ) + 1 ] × 2048 ; converted to hexadecimal

A starting point is change RBIAS to 6.34 kΩ and setting VoD to -8% to further improve margins.