SNLA417 January   2023 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   Abstract
  2. 1Introduction
    1. 1.1 Acronyms
  3. 2TC10 Test Setup
    1. 2.1 Overview
    2. 2.2 Wakeup to Linking Sequence
  4. 3Measurement Summary
    1. 3.1 Complete Timing Diagram
    2. 3.2 Measurement Summary
    3. 3.3 LP1 Wake to Linking Time
  5. 4Timing Measurements
    1. 4.1 LP1 WAKE to INH (T1)
    2. 4.2 LP1 INH to WUP (T2)
    3. 4.3 WUP to PHY INH (T3)
    4. 4.4 PHY INH/Buck EN to Buck nRESET (T4)
    5. 4.5 Buck nRESET/PMIC Enable to MCU nReset (T5)
    6. 4.6 MCU nReset to MDIO Communication (T6 and T7)
    7. 4.7 MDIO Master Configuration + Linking (T8 and T9)
  6. 5Measurement Evaluation
    1. 5.1 Recommendations for Optimizing Variable TC10 Times
      1. 5.1.1 Improving MCU Boot-up Time (T6)
      2. 5.1.2 Improving MDIO State Machine (T7)
      3. 5.1.3 Optimizing MDIO Timeline (T8)
        1. 5.1.3.1 Optimizing Master Configuration by Removing Polling
        2. 5.1.3.2 Optimizing Master Configuration by Improving MDC
      4. 5.1.4 PHY Configuration During Sleep
      5. 5.1.5 Other Configurable Values
    2. 5.2 Alternative TC10 Test
  7. 6Conclusion
  8. 7References

2.2 Wakeup to Linking Sequence

The components and steps that precede the LP1 WAKE pin going high are particularly important because these components and steps decide how fast the system is going to wake up and establish an Ethernet link to begin communication. Overall, the hardware sets a strict limit on the wake-up time. Software also impacts this time, but the time software adds to the wake-up sequence varies with software optimization.

The following steps explain the wakeup to linking sequence:

  1. LP1 WAKE pin goes HIGH, pulling LP1 INH pin HIGH.
  2. LP1 transmits WUP to the LP2.
  3. The LP2 PHY INH pin and the 1st stage enable of the buck (LM62460-Q1) rises.
  4. Buck nRESET and the enable of the PMIC (LP8762-Q1) rises.
  5. nRSTOUT of the PMIC and nRESET of the AM273x-Q1 rises. The MCU boot up starts.
  6. The MCU management data input/output (MDIO) configures the PHY as master. The PHYs begin their link-up sequence.
  7. LED0 on both boards lights up when both PHYs are linked.
Figure 2-1 System Wake-up Sequence

For this test, both PHYs are bootstrapped as slave; however, the AM273x-Q1 configures the PHY of LP2 to be a master so the devices only link after the AM273x-Q1 is on and ready to communicate. This action is to prevent packet loss due to both PHYs being awake and linked without the MCU being ready to receive packets. Therefore, the linking process can occur only after the AM273x-Q1 has finished the boot-up sequence and has configured the PHY as a master through MDIO communication.