SNLA417 January   2023 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   Abstract
  2. 1Introduction
    1. 1.1 Acronyms
  3. 2TC10 Test Setup
    1. 2.1 Overview
    2. 2.2 Wakeup to Linking Sequence
  4. 3Measurement Summary
    1. 3.1 Complete Timing Diagram
    2. 3.2 Measurement Summary
    3. 3.3 LP1 Wake to Linking Time
  5. 4Timing Measurements
    1. 4.1 LP1 WAKE to INH (T1)
    2. 4.2 LP1 INH to WUP (T2)
    3. 4.3 WUP to PHY INH (T3)
    4. 4.4 PHY INH/Buck EN to Buck nRESET (T4)
    5. 4.5 Buck nRESET/PMIC Enable to MCU nReset (T5)
    6. 4.6 MCU nReset to MDIO Communication (T6 and T7)
    7. 4.7 MDIO Master Configuration + Linking (T8 and T9)
  6. 5Measurement Evaluation
    1. 5.1 Recommendations for Optimizing Variable TC10 Times
      1. 5.1.1 Improving MCU Boot-up Time (T6)
      2. 5.1.2 Improving MDIO State Machine (T7)
      3. 5.1.3 Optimizing MDIO Timeline (T8)
        1. 5.1.3.1 Optimizing Master Configuration by Removing Polling
        2. 5.1.3.2 Optimizing Master Configuration by Improving MDC
      4. 5.1.4 PHY Configuration During Sleep
      5. 5.1.5 Other Configurable Values
    2. 5.2 Alternative TC10 Test
  7. 6Conclusion
  8. 7References

Optimizing Master Configuration by Removing Polling

Each MDIO frame is 64 bits since the MDIO data follows Clause 22. The data format for clause 22 is in the following list.

  • 32-bit preamble (optional)
  • 2-bit start
  • 2-bit opcode (Write and Read operations only)
  • 5-bit PHY address
  • 5-bit register address
  • 2-bit turnaround time
  • 16-bit data

Overall, the master configuration sequence in Table 4-1 takes 179 read or write instructions with polling. The MDC was measured to be 3 MHz.

By removing polling, the master configuration time is decreased since polling creates unnecessary read instructions. When removing all unnecessary read instructions, only 90 instructions are needed to configure the PHY as master. Most of these write instructions involve extended registers, which require 4 writes to successfully write to them.

Removing the optional preamble is also beneficial because the preamble is not needed for the read and write transactions. This decreases the size of each MDIO frame to 32 bits.

Δtms_cfg= 90 instructions × 32 bits × (1/3 MHz) = 0.960ms. This is 2.954ms less than the actual time measured.