SNLA438 September   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826E , DP83826I , DP83867CS , DP83867E , DP83867IS , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PROFINET Specification Requirements
  6. 3Ethernet PHY Setup
    1. 3.1 DP83822
      1. 3.1.1 DP83822 Hardware Bootstrap Configurations
      2. 3.1.2 DP83822 Register Configuration
    2. 3.2 DP83826
      1. 3.2.1 DP83826 Hardware Bootstrap Configuration
      2. 3.2.2 DP83826 Register Configuration
    3. 3.3 DP83867
      1. 3.3.1 DP83867 Hardware Bootstrap Configurations
      2. 3.3.2 DP83867 Register Configuration
    4. 3.4 DP83869
      1. 3.4.1 DP83869 Hardware Bootstrap Configurations
      2. 3.4.2 DP83869 Register Configuration
  7. 4Summary
  8. 5References

3.1.1 DP83822 Hardware Bootstrap Configurations

The DP83822 uses certain pins as bootstrap options to place the device into specific modes of operation. The values of these pins are sampled at power up or hardware reset, providing a way to configure the device into a desired mode without the need for software configuration.

GUID-05836162-D064-41F0-8B4A-2AC7F7E8215F-low.gif Figure 3-2 Bootstrap Circuit
Note: The 50 kΩ and 9 kΩ resistors are internal pull-up and pull-down resistors, respectively.
Table 3-1 DP83822 100Base-TX Strapping
DP83822 100Base-TX Strapping Pin RH(kΩ) RL(kΩ) Remarks

PHY Address: 1,

MAC Interface: MII,

10/100 Mbps Full Duplex Advertised,

Copper,

Auto-negotiation Enabled,

Auto-MDIX Enabled,

FLD Enabled,

 COL Open Open

Copper

PHY_ADD0[1]
RX_D0 Open Open PHY_ADD1[0]
RX_D1 Open Open

EEE disable

PHY_ADD2[0]
RX_D2 10 2.49

FLD Enabled

PHY_ADD3[0]
RX_D3 Open Open Auto-Negotiation Enabled
LED_0 Open Open

Advertised Full Duplex

10Base-Te/100Base-TX
LED_1 Open Open No Added Functionality

Do not use Mode 2 & 3
RX_ER Open Open

MII

Auto-MDIX Enable
RX_DV Open Open MII

Table 3-2 DP83822 100Base-FX Strapping
DP83822 100Base-FX Strapping Pin RH(kΩ) RL(kΩ) Remarks

PHY Address: 1,

MAC Interface: MII,

10/100 Mbps Full Duplex Advertised,

Fiber,

Auto-negotiation Enabled,

Auto-MDIX Enabled,

FLD Enabled,

 COL 13 1.96

Fiber Enabled

PHY_ADD0[1]
RX_D0 Open Open PHY_ADD1[0]
RX_D1 Open Open

EEE disable

PHY_ADD2[0]
RX_D2 10 2.49

FLD Enabled

PHY_ADD3[0]
RX_D3 Open Open Auto-Negotiation Enabled
LED_0 Open Open

Advertised Full Duplex

10Base-Te/100Base-FX
LED_1 Open Open

No Added Functionality

Do not use Mode 2 & 3
RX_ER Open Open

MII

Auto-MDIX Enable
RX_DV Open Open MII
Note: PHY_ADD[0..3] determine the PHY's Address. In Table 3-1 and Table 3-2, PHY Address is set to 0b0001.