SNLA443A December   2023  – August 2025 DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83869 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
        1. 2.2.5.1 Configuring Correct Operational Mode
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RGMII Check
      3. 2.4.3 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Operational Mode Clarification
    1. 3.1 Bridge Modes
    2. 3.2 Fiber Configuration
      1. 3.2.1 Fiber Registers
      2. 3.2.2 Media Converter LED Behavior
  7. 4Tools and References
    1. 4.1 Extended Register Access
      1. 4.1.1 Read (No Post Increment) Operation
      2. 4.1.2 Write (No Post Increment) Operation
    2. 4.2 Software and Driver Debug on Linux
      1. 4.2.1 Common Terminal Outputs
  8. 5Summary
  9. 6References
  10. 7Revision History

2.2.5.1 Configuring Correct Operational Mode

The operational mode of the DP83869 is configured through the OPMODE[0], OPMODE[1], and OPMODE[2] straps. A brief summary of each OPMODE configuration is provided in Table 2-4. More information can be found in the Programming section of the data sheet.

To verify DP83869's operational mode, register 0x6E can be read to confirm. Register 0x6E is read-only, meaning the Operational Mode cannot be changed by writing to this register. Software configuration of the DP83869 is possible through register 0x1DF which allows writes to configure the OPMODE. Some operational modes require more register writes than just register 0x1DF, this information is provided in the Register Configuration for Operational Modes Section in the data sheet.

Note: Registers 0x6E and 0x1DF are extended registers and cannot be accessed directly. Please reference Section 4.1.

Table 2-4 Functional Mode Strap Table
PIN NAMESTRAP NAMEPIN #DEFAULTOPMODE[2]OPMODE[1]OPMODE[0]FUNCTIONAL MODES
JTAG_TDO/GPIO_1OPMODE[0]220000RGMII to Copper (1000Base-T/100Base-TX/10Base-Te)
001RGMII to 1000Base-X
RX_D3OPMODE[1]360010RGMII to 100Base-FX
011RGMII-SGMII Bridge Mode
RX_D2OPMODE[2]3501001000Base-T to 1000Base-X
101100Base-Tx to 100Base-FX
110SGMII to Copper (1000Base-T/100Base-TX/10Base-Te)
111JTAG for boundary scan