Reduced Gigabit Media Independent Interface (RGMII) is a 4-bit wide data interface that supports up to 1000Mbps communication between a PHY and MAC. RGMII mode can be enabled via strapping the OPMODE[2:0] pins low, or by writing '000' to register 0x01DF[2:0].

The RGMII signals are summarized below:

Figure 2-15 RGMII Signaling

Reference the waveforms in this section to verify the expected MAC data and clock signals for RGMII in shift and align modes. To capture data and clock signals, measure close to the receiver end. Note the following requirements for selecting the correct delay mode:

RX_D[3:0] Data Aligned with RX_CLK

For the PHY set in RX align mode in 10/100Mbps, probe the clock and data signals on the MAC end and compare to the reference waveforms shown below.

Figure 2-16 10Mbps Data Aligned With RX_CLK

Verify the frequency of the clock (C2) as 2.5 MHz and the data (C1) being sampled at the rising edge of the clock.

Figure 2-17 100Mbps Data Aligned With RX_CLK

Verify the frequency of the clock (C2) as 25 MHz and the data (C1) being sampled at the rising edge of the clock.

Figure 2-18 10Mbps Data and Clock Delay in Align Mode

Verify the delay between clock and data is <500ps in align mode.

RX_D[3:0] Data and RX_CLK in Shift Mode

For the PHY set in RX shift mode (0x32) in 10/100Mbps, probe the clock and data signals on the MAC end and compare to the following reference waveforms.

Figure 2-19 10Mbps Data and RX_CLK in Shift Mode (4ns Programmed Delay)

Verify the delay between clock and data is >1ns in shift mode. The programmed delay is relative to the clock's initial position in aligned mode. Measuring the difference in the clock's position before and after setting shift mode yields a value closer to the programmed delay.

TX_D[3:0] and TX_CLK in Shift and Align Mode

With the PHY set in TX shift or align mode, probe the data and clock signals on the PHY end and verify the timing requirements below are met: