SNLA443A December   2023  – August 2025 DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83869 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
        1. 2.2.5.1 Configuring Correct Operational Mode
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RGMII Check
      3. 2.4.3 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Operational Mode Clarification
    1. 3.1 Bridge Modes
    2. 3.2 Fiber Configuration
      1. 3.2.1 Fiber Registers
      2. 3.2.2 Media Converter LED Behavior
  7. 4Tools and References
    1. 4.1 Extended Register Access
      1. 4.1.1 Read (No Post Increment) Operation
      2. 4.1.2 Write (No Post Increment) Operation
    2. 4.2 Software and Driver Debug on Linux
      1. 4.2.1 Common Terminal Outputs
  8. 5Summary
  9. 6References
  10. 7Revision History

4.1 Extended Register Access

The DP83869HM's Serial Management Interface (SMI) function supports read or write access to the extended register set using registers REGCR (0x0D) and ADDAR (0x0E) and the MDIO Manageable Device (MMD) indirect method defined in IEEE 802.3ah Draft for clause 22 for accessing the clause 45 extended register set.

The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the indirect method, except for register REGCR (0x0D) and ADDAR (0x0E), which is accessed only using the normal MDIO transaction. The SMI function ignores indirect accesses to these registers.

REGCR (0x0D) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR (0x0E) register to the appropriate MMD.

The PHY’S supports one MMD device address. The vendor-specific device address DEVAD[4:0] = 11111 is used for general MMD register accesses.

All accesses through registers REGCR and ADDAR must use the correct DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data with post increment on read and writes (10), and data with post increment on writes only (11).

Table 4-1 REGCR DEVAD Functions
REGCR[15:14] Function
00

Accesses to register ADDAR modify the extended register ‘set address’ register. This address register must always be initialized to access any of the registers within the extended register set.
01 Accesses to register ADDAR access the register within the extended register set selected by the value in the address register.
10 Access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented.
11 Access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged.

The following sections describe how to perform operations on the extended register set using register REGCR and ADDAR. The descriptions use the device address for general MMD register accesses (DEVAD[4:0] = 11111).