SNLA443A December   2023  – August 2025 DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83869 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
        1. 2.2.5.1 Configuring Correct Operational Mode
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RGMII Check
      3. 2.4.3 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Operational Mode Clarification
    1. 3.1 Bridge Modes
    2. 3.2 Fiber Configuration
      1. 3.2.1 Fiber Registers
      2. 3.2.2 Media Converter LED Behavior
  7. 4Tools and References
    1. 4.1 Extended Register Access
      1. 4.1.1 Read (No Post Increment) Operation
      2. 4.1.2 Write (No Post Increment) Operation
    2. 4.2 Software and Driver Debug on Linux
      1. 4.2.1 Common Terminal Outputs
  8. 5Summary
  9. 6References
  10. 7Revision History

2.2.6.1 Read and Check Register Values

Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options. An example of expected register values for PHY operation and link in 100/1000Mbps with auto-negotiation enabled are shown in Table 2-5.

Table 2-5 Example Register Values on Link up
Register Address Register Value Comments
100Mbps 1000Mbps
0x0000 1140 1140 Auto-negotiation enabled
0x0001 796D 796D Link established, Auto-negotiation status
0x0004 01E1 01E1 10/100Mbps advertisement
0x0009 0000 0300 1000Mbps advertisement
0x0011 4F02 BC02 Link properties. With the PHY linked in a given speed, use these values as a reference to identify any variance from the expected operation. Note that not all registers need to be the same as what is shown in this table.

Example: After powering and linking the PHY in 1000Mbps, Reg 0x11 contains the value 0xBC02. This confirms:

  • 1000Mbps Mode
  • Full-Duplex
  • Auto-Negotiation is complete
  • Link established
If register access is not readily available in the application, USB-2-MDIO GUI is available from TI and can be used with an MSP430F5529™ Launchpad, purchasable through the TI eStore. The GUI supports reading and writing registers, running script files, and can be used with the DP83869HM and the other devices in TI's Ethernet portfolio. USB-2-MDIO User's Guide and GUI are available for download.