SNLA443A December   2023  – August 2025 DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83869 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
        1. 2.2.5.1 Configuring Correct Operational Mode
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RGMII Check
      3. 2.4.3 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Operational Mode Clarification
    1. 3.1 Bridge Modes
    2. 3.2 Fiber Configuration
      1. 3.2.1 Fiber Registers
      2. 3.2.2 Media Converter LED Behavior
  7. 4Tools and References
    1. 4.1 Extended Register Access
      1. 4.1.1 Read (No Post Increment) Operation
      2. 4.1.2 Write (No Post Increment) Operation
    2. 4.2 Software and Driver Debug on Linux
      1. 4.2.1 Common Terminal Outputs
  8. 5Summary
  9. 6References
  10. 7Revision History

2.5.3 Transmitting and Receiving Packets with BIST

The device incorporates an internal PRBS Built-in Self-Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. BIST can be performed using various loopback modes to isolate any issues to specific parts of the data path. The BIST generates packetized data with variable content and IPG.

If generating and checking packets with the MAC is not possible, use PRBS packet generation and checking functionality to verify the data path. Perform reverse loopback with PRBS and a working link partner as follows:

  1. Power and connect the PHY to a link partner.

  2. Enable PRBS packet generation on the PHY (write Reg 0x0016 = 0xF000).

  3. Enable reverse loopback on the link partner (If Link Partner is DP83869 write Reg 0x0016 = 0x0020).

  4. Wait at least one second, then check PRBS lock status on the PHY by reading register 0x0017[11].

If register 0x0017[11] is high, the data path through PHY → MDI is valid. If this test does not pass, the issue can be on the PHY's internal data path or the MDI. To verify the internal data path, perform PRBS with analog loopback using the following procedure:

  1. Write register 0x001F = 0x8000 //PHY reset

  2. Write register 0x0000 = 0x0140 //Disable Auto-neg, force 1000Mbps

  3. Write register 0x0016 = 0x0008 //Enable Analog loopback, use 100Ω MDI terminations

  4. Write register 0x0016 = 0xF008 //Enable PRBS generator

  5. Read register 0x0017[11] //Should be high for PRBS locked

  6. Read register 0x0072[7:0] //Should be 0x00 for no errors

If the internal data path is valid the issue is isolated to the MDI or the link partner.