SNLA487 May   2025 DP83826AE , DP83826AI

 

  1.   1
  2.   KSZ8081MNX/RNB to DP83826A System Rollover
  3.   Trademarks
  4. 1Purpose
  5. 2Required Changes
    1. 2.1 Strap Resistor Value
    2. 2.2 External Capacitor on Pin 2
    3. 2.3 Duplex Strap on Pin 16 (DP83826A Basic Mode)
    4. 2.4 Selecting 10M with Auto-Negotiation Enabled (DP83826A Basic Mode)
    5. 2.5 Configuring LED_1 for Tx and Rx Activity for EtherCAT Slave (DP83826A Basic Mode)
    6. 2.6 Thermal Pad Adjustments in Layout
    7. 2.7 Physical Layer ID Register
  6. 3Potential Changes
    1. 3.1 MDIO Pull-Up Resistor on Pin 11
    2. 3.2 MDIO Register Writes
    3. 3.3 Capacitors on Center Tap of Magnetics
  7. 4Informational Changes
  8. 5Pinout Mapping
    1. 5.1 Pin Mapping
  9. 6DP83826A Strap Configurations
    1. 6.1 Bootstrap Configurations

5.1 Pin Mapping

The table below shows the pinout mapping between the DP83826A and KSZ8081MNX/RNB. For more details on the pin mapping as well as any updates made, see the DP83826A data sheet.

Table 5-1 Pinout Mapping
Pin No.KSZ8081MNX/RNB Pin FunctionsDP83826A BASIC Mode Pin FunctionsDP83826A ENHANCED Mode Pin Functions
1GNDMode SelectMode Select
2VDD_1.2CEXTCEXT
3VDDA_3.3VDDA3V3VDDA3V3
4RXMRD_MRD_M
5RXPRD_PRD_P
6TXMTD_MTD_M
7TXPTD_PTD_P
8XOXOXO
9XIXI/50MHzInXI/50MHzIn
10REXTRBIASRBIAS
11MDIOMDIOMDIO
12MDCMDCMDC
13PHYAD0 (RXD3)RX_D3RX_D3
14PHYAD1 (RXD2)RX_D2RX_D2
15RXD1/ PHYAD2RX_D1RX_D1
16RXD0/ DUPLEXRX_D0RX_D0
17VDDIOVDDIOVDDIO
18RXDV/ CONFIG2RX_DV/CRS _DVRX_DV/CRS _DV
19RXC/ B-CAST_OFFRX_CLK/50 MHz_OutputRX_CLK/50 MHz_RMII
20RXER/ ISORX_ERRX_ER
21INTRP/ NAND_Tree#INTPWRDN/INT
22TXCTX_CLKTX_CLK
23TXENTX_ENTX_EN
24TXD0TX_D0TX_D0
25TXD1TX_D1TX_D1
26TXD2TX_D2TX_D2
27TXD3TX_D3TX_D3
28COL/ CONFIG0COLCOL/LED2/GPIO
29CRS/ CONFIG1CRSCRS/LED3
30LED0/ NWAYEN ILED0LED0
31LED1/ SPEEDLED1LED1
32RST#RST_NRST_N