SNLS504G October   2015  – June 2026 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  SGMII Timing
    10. 6.10 RGMII Timing
    11. 6.11 DP83867E Start of Frame Detection Timing
    12. 6.12 DP83867IS/CS Start of Frame Detection Timing
    13. 6.13 Timing Diagrams
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Leader Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Follower Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Serial GMII (SGMII)
        2. 7.4.1.2 Reduced GMII (RGMII)
          1. 7.4.1.2.1 1000Mbps Mode Operation
          2. 7.4.1.2.2 1000Mbps Mode Timing
          3. 7.4.1.2.3 10Mbps and 100Mbps Mode
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Leader and Follower Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Drop (FLD)
        4. 7.4.6.4 Fast Link Detect
        5. 7.4.6.5 Speed Optimization
        6. 7.4.6.6 Mirror Mode
        7. 7.4.6.7 Interrupt
        8. 7.4.6.8 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
        5. 7.5.5.5 PCS Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
  9. 8 Registers
    1.     99
      1. 8.1.1   Basic Mode Control Register (BMCR)
      2. 8.1.2   Basic Mode Status Register (BMSR)
      3. 8.1.3   PHY Identifier Register #1 (PHYIDR1)
      4. 8.1.4   PHY Identifier Register #2 (PHYIDR2)
      5. 8.1.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7   Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 8.1.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 8.1.10  1000BASE-T Configuration Register (CFG1)
      11. 8.1.11  Status Register 1 (STS1)
      12. 8.1.12  Extended Register Addressing
        1. 8.1.12.1 Register Control Register (REGCR)
        2. 8.1.12.2 Address or Data Register (ADDAR)
      13. 8.1.13  1000BASE-T Status Register (1KSCR)
      14. 8.1.14  PHY Control Register (PHYCR)
      15. 8.1.15  PHY Status Register (PHYSTS)
      16. 8.1.16  MII Interrupt Control Register (MICR)
      17. 8.1.17  Interrupt Status Register (ISR)
      18. 8.1.18  Configuration Register 2 (CFG2)
      19. 8.1.19  Receiver Error Counter Register (RECR)
      20. 8.1.20  BIST Control Register (BISCR)
      21. 8.1.21  Status Register 2 (STS2)
      22. 8.1.22  LED Configuration Register 1 (LEDCR1)
      23. 8.1.23  LED Configuration Register 2 (LEDCR2)
      24. 8.1.24  LED Configuration Register (LEDCR3)
      25. 8.1.25  Configuration Register 3 (CFG3)
      26. 8.1.26  Control Register (CTRL)
      27. 8.1.27  Testmode Channel Control (TMCH_CTRL)
      28. 8.1.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 8.1.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 8.1.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 8.1.31  Configuration Register 4 (CFG4)
      32. 8.1.32  RGMII Control Register (RGMIICTL)
      33. 8.1.33  RGMII Control Register 2 (RGMIICTL2)
      34. 8.1.34  SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
      35. 8.1.35  100BASE-TX Configuration (100CR)
      36. 8.1.36  Viterbi Module Configuration (VTM_CFG)
      37. 8.1.37  Skew FIFO Status (SKEW_FIFO)
      38. 8.1.38  Strap Configuration Status Register 1 (STRAP_STS1)
      39. 8.1.39  Strap Configuration Status Register 2 (STRAP_STS2)
      40. 8.1.40  BIST Control and Status Register 1 (BICSR1)
      41. 8.1.41  BIST Control and Status Register 2 (BICSR2)
      42. 8.1.42  BIST Control and Status Register 3 (BICSR3)
      43. 8.1.43  BIST Control and Status Register 4 (BICSR4)
      44. 8.1.44  Configuration for Receiver's Equalizer (CRE)
      45. 8.1.45  RGMII Delay Control Register (RGMIIDCTL)
      46. 8.1.46  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      47. 8.1.47  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      48. 8.1.48  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      49. 8.1.49  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      50. 8.1.50  Configuration of Receiver's LPF (CRLPF)
      51. 8.1.51  Enable Control of Receiver's Equalizer (ECRE)
      52. 8.1.52  PLL Clock-out Control Register (PLLCTL)
      53. 8.1.53  SGMII Control Register 1 (SGMIICTL1)
      54. 8.1.54  Transmitter Control Register (ANA_LD_DATA_CTRL)
      55. 8.1.55  DSP Configuration Register 3 (DSP_CFG3)
      56. 8.1.56  Sync FIFO Control (SYNC_FIFO_CTRL)
      57. 8.1.57  DSP Hybrid Configuration Register 2 (DSP_HYBRID_CFG2)
      58. 8.1.58  Loopback Configuration Register (LOOPCR)
      59. 8.1.59  DSP Configuration (DSP_CONFIG)
      60. 8.1.60  DSP Select Register 0 (DSP_SEL0)
      61. 8.1.61  DSP Select Register 1 (DSP_SEL1)
      62. 8.1.62  DSP Select Register 2 (DSP_SEL2)
      63. 8.1.63  DSP Follower Select Register 0 (DSP_FLR_SEL0)
      64. 8.1.64  DSP Follower Select Register 3 (DSP_FLR_SEL3)
      65. 8.1.65  DSP Follower Timing Loop Register 1 (DSP_FLR_TLOOP1)
      66. 8.1.66  DSP Follower Timing Loop Register 2 (DSP_FLR_TLOOP2)
      67. 8.1.67  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      68. 8.1.68  Receive Configuration Register (RXFCFG)
      69. 8.1.69  Receive Status Register (RXFSTS)
      70. 8.1.70  Pattern Match Data Register 1 (RXFPMD1)
      71. 8.1.71  Pattern Match Data Register 2 (RXFPMD2)
      72. 8.1.72  Pattern Match Data Register 3 (RXFPMD3)
      73. 8.1.73  SecureOn Pass Register 2 (RXFSOP1)
      74. 8.1.74  SecureOn Pass Register 2 (RXFSOP2)
      75. 8.1.75  SecureOn Pass Register 3 (RXFSOP3)
      76. 8.1.76  Receive Pattern Register 1 (RXFPAT1)
      77. 8.1.77  Receive Pattern Register 2 (RXFPAT2)
      78. 8.1.78  Receive Pattern Register 3 (RXFPAT3)
      79. 8.1.79  Receive Pattern Register 4 (RXFPAT4)
      80. 8.1.80  Receive Pattern Register 5 (RXFPAT5)
      81. 8.1.81  Receive Pattern Register 6 (RXFPAT6)
      82. 8.1.82  Receive Pattern Register 7 (RXFPAT7)
      83. 8.1.83  Receive Pattern Register 8 (RXFPAT8)
      84. 8.1.84  Receive Pattern Register 9 (RXFPAT9)
      85. 8.1.85  Receive Pattern Register 10 (RXFPAT10)
      86. 8.1.86  Receive Pattern Register 11 (RXFPAT11)
      87. 8.1.87  Receive Pattern Register 12 (RXFPAT12)
      88. 8.1.88  Receive Pattern Register 13 (RXFPAT13)
      89. 8.1.89  Receive Pattern Register 14 (RXFPAT14)
      90. 8.1.90  Receive Pattern Register 15 (RXFPAT15)
      91. 8.1.91  Receive Pattern Register 16 (RXFPAT16)
      92. 8.1.92  Receive Pattern Register 17 (RXFPAT17)
      93. 8.1.93  Receive Pattern Register 18 (RXFPAT18)
      94. 8.1.94  Receive Pattern Register 19 (RXFPAT19)
      95. 8.1.95  Receive Pattern Register 20 (RXFPAT20)
      96. 8.1.96  Receive Pattern Register 21 (RXFPAT21)
      97. 8.1.97  Receive Pattern Register 22 (RXFPAT22)
      98. 8.1.98  Receive Pattern Register 23 (RXFPAT23)
      99. 8.1.99  Receive Pattern Register 24 (RXFPAT24)
      100. 8.1.100 Receive Pattern Register 25 (RXFPAT25)
      101. 8.1.101 Receive Pattern Register 26 (RXFPAT26)
      102. 8.1.102 Receive Pattern Register 27 (RXFPAT27)
      103. 8.1.103 Receive Pattern Register 28 (RXFPAT28)
      104. 8.1.104 Receive Pattern Register 29 (RXFPAT29)
      105. 8.1.105 Receive Pattern Register 30 (RXFPAT30)
      106. 8.1.106 Receive Pattern Register 31 (RXFPAT31)
      107. 8.1.107 Receive Pattern Register 32 (RXFPAT32)
      108. 8.1.108 Receive Pattern Byte Mask Register 1 (RXFPBM1)
      109. 8.1.109 Receive Pattern Byte Mask Register 2 (RXFPBM2)
      110. 8.1.110 Receive Pattern Byte Mask Register 3 (RXFPBM3)
      111. 8.1.111 Receive Pattern Byte Mask Register 4 (RXFPBM4)
      112. 8.1.112 Receive Pattern Control (RXFPATC)
      113. 8.1.113 10M SGMII Configuration (10M_SGMII_CFG)
      114. 8.1.114 I/O Configuration (IO_MUX_CFG)
      115. 8.1.115 GPIO Mux Control Register (GPIO_MUX_CTRL)
      116. 8.1.116 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      117. 8.1.117 TDR Threshold Configuration Register 1 (TDR_THR_CFG1)
      118. 8.1.118 TDR Threshold Configuration Register 2 (TDR_THR_CFG2)
      119. 8.1.119 TDR General Configuration Register 5 (TDR_GEN_CFG5)
      120. 8.1.120 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      121. 8.1.121 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      122. 8.1.122 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      123. 8.1.123 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      124. 8.1.124 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      125. 8.1.125 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      126. 8.1.126 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      127. 8.1.127 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      128. 8.1.128 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      129. 8.1.129 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      130. 8.1.130 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      131. 8.1.131 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      132. 8.1.132 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      133. 8.1.133 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      134. 8.1.134 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      135. 8.1.135 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      136. 8.1.136 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      137. 8.1.137 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      138. 8.1.138 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      139. 8.1.139 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      140. 8.1.140 TDR General Status (TDR_GEN_STATUS)
      141. 8.1.141 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      142. 8.1.142 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
      143. 8.1.143 DSP Leader Step 4 Register (DSP_LDR_STEP4)
      144. 8.1.144 DSP Follower Step 4 Register (DSP_FLR_STEP4)
      145. 8.1.145 DSP Follower Step 5 Register (DSP_FLR_STEP5)
      146. 8.1.146 DSP Follower Step 6&7 Register (DSP_FLR_STEP67)
      147. 8.1.147 Programmable Gain Register (PROG_GAIN)
      148. 8.1.148 MMD3 PCS Control Register (MMD3_PCS_CTRL)
      149. 8.1.149 Mean Square Error Channel A Register (MSE_A)
      150. 8.1.150 Mean Square Error Channel B Register (MSE_B)
      151. 8.1.151 Mean Square Error Channel C Register (MSE_C)
      152. 8.1.152 Mean Square Error Channel D Register (MSE_D)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Cable Line Driver
        2. 9.2.1.2 Clock In (XI) Recommendation
        3. 9.2.1.3 Crystal Recommendations
        4. 9.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MAC Interface
          1. 9.2.2.1.1 SGMII Layout Guidelines
          2. 9.2.2.1.2 RGMII Layout Guidelines
        2. 9.2.2.2 Media Dependent Interface (MDI)
          1. 9.2.2.2.1 MDI Layout Guidelines
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.1 Design Requirements

The design requirements for the DP83867 are:

  • VDDA2P5 = 2.5V
  • VDD1P0 = 1V
  • VDDIO = 3.3V, 2.5V, or 1.8V
  • Clock Input = 25MHz