SNLS505H July   2016  – July 2026 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, Power-Up Timing
    7. 6.7  Timing Requirements, Power-Up With Unstable XI Clock
    8. 6.8  Timing Requirements, Reset Timing
    9. 6.9  Timing Requirements, Serial Management Timing
    10. 6.10 Timing Requirements, 100Mbps MII Transmit Timing
    11. 6.11 Timing Requirements, 100Mbps MII Receive Timing
    12. 6.12 Timing Requirements, 10Mbps MII Transmit Timing
    13. 6.13 Timing Requirements, 10Mbps MII Receive Timing
    14. 6.14 Timing Requirements, RMII Transmit Timing
    15. 6.15 Timing Requirements, RMII Receive Timing
    16. 6.16 Timing Requirements, RGMII
    17. 6.17 Normal Link Pulse Timing
    18. 6.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
    19. 6.19 10BASE-Te Jabber Timing
    20. 6.20 100BASE-TX Transmit Latency Timing
    21. 6.21 100BASE-TX Receive Latency Timing
    22. 6.22 Timing Diagrams
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Energy Efficient Ethernet
        1. 7.3.1.1 EEE Overview
        2. 7.3.1.2 EEE Negotiation
      2. 7.3.2 Wake-on-LAN Packet Detection
        1. 7.3.2.1 Magic Packet Structure
        2. 7.3.2.2 Magic Packet Example
        3. 7.3.2.3 Wake-on-LAN Configuration and Status
      3. 7.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 7.3.4 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1  MAC Interfaces
        1. 7.4.1.1 Media Independent Interface (MII)
        2. 7.4.1.2 Reduced Media Independent Interface (RMII)
        3. 7.4.1.3 RMII Repeater Mode
        4. 7.4.1.4 Reduced Gigabit Media Independent Interface (RGMII)
      2. 7.4.2  Serial Management Interface
        1. 7.4.2.1 Extended Register Space Access
        2. 7.4.2.2 Write Address Operation
        3. 7.4.2.3 Read Address Operation
        4. 7.4.2.4 Write (No Post Increment) Operation
        5. 7.4.2.5 Read (No Post Increment) Operation
        6. 7.4.2.6 Write (Post Increment) Operation
        7. 7.4.2.7 Read (Post Increment) Operation
        8. 7.4.2.8 Example Write Operation (No Post Increment)
        9. 7.4.2.9 Example Read Operation (No Post Increment)
      3. 7.4.3  100BASE-TX
        1. 7.4.3.1 100BASE-TX Transmitter
          1. 7.4.3.1.1 Code-Group Encoding and Injection
          2. 7.4.3.1.2 Scrambler
          3. 7.4.3.1.3 NRZ to NRZI Encoder
          4. 7.4.3.1.4 Binary to MLT-3 Converter
        2. 7.4.3.2 100BASE-TX Receiver
      4. 7.4.4  100BASE-FX
        1. 7.4.4.1 100BASE-FX Transmit
        2. 7.4.4.2 100BASE-FX Receive
      5. 7.4.5  10BASE-Te
        1. 7.4.5.1 Squelch
        2. 7.4.5.2 Normal Link Pulse Detection and Generation
        3. 7.4.5.3 Jabber
        4. 7.4.5.4 Active Link Polarity Detection and Correction
      6. 7.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 7.4.7  Auto-MDIX Resolution
      8. 7.4.8  Loopback Modes
        1. 7.4.8.1 Near-End Loopback
        2. 7.4.8.2 MII Loopback
        3. 7.4.8.3 PCS Loopback
        4. 7.4.8.4 Digital Loopback
        5. 7.4.8.5 Analog Loopback
        6. 7.4.8.6 Far-End (Reverse) Loopback
      9. 7.4.9  BIST Configurations
      10. 7.4.10 Cable Diagnostics
        1. 7.4.10.1 TDR
      11. 7.4.11 Fast Link Down Functionality
    5. 7.5 Programming
      1. 7.5.1 Hardware Bootstrap Configurations
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
  9. 8 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Characteristics
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
          1. 9.4.1.3.1 Transformer Recommendations
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.3 Power Supply Recommendations

The DP83822 is capable of operating with a wide range of I/O supply voltages (3.3V, 2.5V, or 1.8V) along with any of the two analog supply options (3.3V or 1.8V). Please note that input pins must not be driven until VDDIO and AVD are stable.

Figure 9-4 shows the recommended power supply decoupling network.

DP83822HF DP83822IF DP83822H DP83822I Power Connections
A. The smallest value is placed closest to the pin
Figure 9-5 Power Connections
Note:

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.