SNLS676B May   2022  – July 2026 DP83TC813R-Q1 , DP83TC813S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep Ack
      6. 7.4.6  Sleep Request
      7. 7.4.7  Sleep Fail
      8. 7.4.8  Sleep
      9. 7.4.9  Wake-Up
      10. 7.4.10 TC10 System Example
      11. 7.4.11 Media Dependent Interface
        1. 7.4.11.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.11.2 Auto-Polarity Detection and Correction
        3. 7.4.11.3 Jabber Detection
        4. 7.4.11.4 Interleave Detection
      12. 7.4.12 MAC Interfaces
        1. 7.4.12.1 Media Independent Interface
        2. 7.4.12.2 Reduced Media Independent Interface
        3. 7.4.12.3 Reduced Gigabit Media Independent Interface
        4. 7.4.12.4 Serial Gigabit Media Independent Interface
      13. 7.4.13 Serial Management Interface
        1. 7.4.13.1 Direct Register Access
        2. 7.4.13.2 Extended Register Space Access
        3. 7.4.13.3 Write Operation (No Post Increment)
        4. 7.4.13.4 Read Operation (No Post Increment)
        5. 7.4.13.5 Write Operation (Post Increment)
        6. 7.4.13.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC813 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from Revision A (December 2025) to Revision B (July 2026)

  • Added information regarding pull-up to VDDIO for MDIO in Serial Management InterfaceGo
  • Updated Pin Domain table to include information regarding input pins and external pull-up resistorsGo
  • Updated order of encoding cases in RGMII Transmit EncodingGo
  • Updated order of encoding cases in RGMII Receive EncodingGo
  • Updated register address rangeGo
  • Updated LED1 configuration informationGo
  • Updated register address range in MMD Register Space DivisionGo

Changes from Revision * (May 2022) to Revision A (December 2025)

  • Updated Pin 22 description to include programming settings for RX_DV and CRS_DV in the Pin Configuration and Functions sectionGo
  • Updated MDIO pin description to include link to Compliance Test Modes section in the Pin Configuration and Functions sectionGo
  • Updated the CLKOUT frequency to be 50MHz in RMII Follower mode in the Pin Configuration and Functions sectionGo
  • Updated Pin 9 and Pin 21 pin descriptions and package label in the Pin Configuration and Functions section Go
  • Added line to CLKOUT/GPIO2 description about which registers to program to disable switching in the Pin Configuration and Functions sectionGo
  • Removed supply ramp delay offset for all supplies in the Timing Requirements sectionGo
  • Updated the Power-Up Timing figure in the Timing Diagrams sectionGo
  • Added corrections to the TDR description and deleted Register 0x310, Bit 8 in the Time Domain Reflectometry sectionGo
  • Updated and corrected order of register writes for packet generation in the BIST and Loopback Modes sectionGo
  • Clarified register reads for checking incoming data on the MAC sideGo
  • Updated 100BASE-T1 Leader and 100BASE-T1 Follower ConfigurationGo
  • Added corrections to the RGMII Transmit Encoding table for Normal Data Transmission and Transmit Error PropagationGo
  • Updated Bootstraps: RX_DV pin number; corrected to 22Go
  • Updated PHY Address Bootstraps: Binary values corrected to match hex settings Go
  • Added corrections to the LED Configuration section and LED pin descriptionGo
  • Clarified and updated Bit Descriptions throughout the Registers Go
  • Added clarification to Register 0x1834 Bit DescriptionGo
  • Updated RMII Follower typical application diagram for correct XI configuration in the Typical Applications sectionGo
  • Updated RGMII Typical Application diagram to include 25MHz input in the Power Supply Recommendations sectionGo