SNLU334 December   2023 DS320PR410

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  DS320PR410 5-Level I/O Control Inputs
    2. 2.2  DS320PR410 Modes of Operation
    3. 2.3  DS320PR410 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR410 Equalization Control
    5. 2.5  DS320PR410 RX Detect State Machine
    6. 2.6  DS320PR410 DC Gain Control
    7. 2.7  DS320PR410 EVM Global Controls
    8. 2.8  DS320PR410-RSC-EVM Downstream Devices Control
    9. 2.9  DS320PR410-RSC-EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)
  9. 3Implementation Results
    1. 3.1 Test Setup and Results
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6References

2.7 DS320PR410 EVM Global Controls

Table 3-7 shows DS320PR410-RSC-EVM global controls that affect all devices on the board.

Table 2-7 EVM Global Controls
COMPONENTNAMEFUNCTION / DESCRIPTION
J14x2 HeaderMODE control tied to MODE pins of all eight DS320PR410 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus / I2C Primary Mode (EEPROM Mode)
L2: SMBus / IC Secondary Mode
L3: Reserved
L4: Reserved
J24x2 Header

RX_DET control tied to RX_DET pins of all eight DS320PR410 devices on the EVM


L0: RX Detect state machine disabled on all devices
L1: RX Detect state machine enabled on all devices (3 valid detections needed)
L2: RX Detect state machine enabled on all devices (2 valid detections needed)
L3: Reserved
L4: RX Detect state machine enabled on all devices (1 valid detection needed) - Default
J35x2 HeaderSMBus / I2C interface. All eight DS320PR410 devices on the EVM are on the same bus and can be accessed through this interface.
J43x2 HeaderPWDN control tied to PD pins of all eight DS320PR410 devices on the EVM. Remove shunt on J6 when using J4 to control PWDN.
PWDN tied to GND: All devices enabled (Default)
PWDN tied to PERST_INV: All device PD pins controlled by inverted PCIe Reset (PERST#)
PWDN tied to 3.3V_REG: All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN control (optional for PCIe use case)
J53x1 HeaderAccess point to the WP (write protect) pin of the onboard EEPROM devices.
WP tied to GND: I2C Access to the EEPROM enabled
WP floating: I2C Access to the EEPROM disabled (Default)
J62x1 HeaderAlternative PWDN Control. Remove shunt on J4 when using J6 to control PWDN.
PWDN floating: Use J4 for the PWDN control (Default)
PWDN tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case).
J7, J8, J9, J103x1 HeadersPCIe PRSNT Signal Controls
Tie pins 1-2 on J7, J8, J9, and J10: Allow support any PCIe bus width (Default)
Tie pins 2-3 of J7, leave J8, J9, and J10 floating: Force x1 PCIe bus width.
Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4 PCIe bus width.
Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe bus width.
Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus width.
J112x1 HeaderOnboard regulator input. Apply 12 V when using the EVM as a standalone system. DO NOT APPLY power if plugging the EVM into a system as the power is provided through the gold finger connector (CONN1).
J122x1 HeaderAccess point to the GND reference.
J132x1 HeaderOnboard 3.3 V output.
J38 3x1 Header Select I2C adapter to plug into Connector J3.
Tie pins 1-2 for TI USB2ANY Adapter
Tie pins 2-3 for Aardvark Adapter (Default)
Select the appropriate jumper position for the selected adapter to avoid damaging the EVM.
J41 3x1 Header READ_EN_N select
Tie pins 1-2 to tie READ_EN_N to GND and initiate EEPROM read (EEPROM mode only) - Default
Tie pins 2-3 to tie READ_EN_N to disable EEPROM read
J44 2x1 Header SMDAT header to connect global SMBus Data line (Pin 1) to local SMDAT/SDA (Pin 2). Remove shunt to disconnect global SMDAT from local SMDAT/SDA.
J45 2x1 Header SMCLK header to connect global SMBus Clock line (Pin 1) to local SMCLK/SCL (Pin 2). Remove shunt to disconnect global SMCLK from local SMCLK/SCL.