SNLU334 December   2023 DS320PR410

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1  DS320PR410 5-Level I/O Control Inputs
    2. 2.2  DS320PR410 Modes of Operation
    3. 2.3  DS320PR410 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR410 Equalization Control
    5. 2.5  DS320PR410 RX Detect State Machine
    6. 2.6  DS320PR410 DC Gain Control
    7. 2.7  DS320PR410 EVM Global Controls
    8. 2.8  DS320PR410-RSC-EVM Downstream Devices Control
    9. 2.9  DS320PR410-RSC-EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus / I2C Secondary Mode)
  9. 3Implementation Results
    1. 3.1 Test Setup and Results
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6References

2.10 Quick-Start Guide (Pin Mode)

Check that the shunts are at the following positions as follows:
  1. The redrivers are configured to operate in Pin Mode (MODE pins tied to L0 using J1 header).
  2. RX Detect state machine of all redrivers is enabled by leaving J2 open (L4 - floating).
  3. The redrivers are enabled (PWDN pins tied to GND by placing a shunt between pins 5-6 on the J4 header). Alternatively, for PCIe sideband signal control, the PWDN pins can be driven by PCIe Present (PRSNT1#) signal by leaving J4 open and placing a shunt across pins 1 and 2 of J6, or by inverted PCIe Reset (PERST#) signal by placing a shunt between pins 3-4 on J4 and by leaving J6 open.
  4. The redrivers are connected to RX_DET and GAIN using the dual function pins at headers J17-J24 and J29-J36 in Table 3-7. Set the shunts for these headers to connect pins 1-2.
  5. The board is configured for any PCIe bus width (PRSNTx# signal controls set as 'default' in Table 3-7 using J7, J8, J9 and J10 headers). Shunts need to be placed between pins 1-2 on headers J7, J8, J9, and J10.
  6. DC Gain of all redrivers is set to 0 dB by leaving J14 open for the downstream redrivers and by leaving J26 open for the upstream redrivers.
  7. EQ level of the RX CTLEs of all redrivers is set to 10 dB at 16 GHz by using J15 and J16 for the downstream redrivers and J27 and J28 for the upstream redrivers (EQ1 = L2, EQ0 = L0).
  8. If necessary, adjust EQ levels of the downstream redrivers, or upstream redrivers, or both, by arranging shunts on J15 and J16 for downstream redrivers and J27 and J28 for the upstream redrivers.
  9. Plug the EVM into a PCIe x16 server motherboard slot. Make sure the motherboard is powered down before installing the EVM or configured for hot-plug operation.
  10. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
  11. Power-up the motherboard.