SNOS631E November   1994  – March 2025 LMC6061 , LMC6062 , LMC6062-MIL , LMC6064

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: LMC6061
    5. 5.5 Thermal Information: LMC6062
    6. 5.6 Thermal Information: LMC6064
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Application and Implementation
    1. 6.1 Applications Information
      1. 6.1.1 Amplifier Topology
      2. 6.1.2 Compensating For Input Capacitance
      3. 6.1.3 Capacitive Load Tolerance
      4. 6.1.4 Latchup
    2. 6.2 Typical Applications
      1. 6.2.1 Instrumentation Amplifier
      2. 6.2.2 Low-Leakage Sample-and-Hold
      3. 6.2.3 1Hz Square-Wave Oscillator
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
        1. 6.3.1.1 Printed Circuit Board Layout For High Impedance Work
      2. 6.3.2 Layout Example
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

6.1.4 Latchup

CMOS devices tend to be susceptible to latchup due to internal parasitic silicon controlled rectifier (SCR) effects. The input and output (I/O) pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC606x are designed to withstand 100mA surge current on the I/O pins. Use a resistive method to isolate any capacitance from supplying excess current to the I/O pins. In addition, like a SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins also inhibits latchup susceptibility.