SNOSD74C May   2019  – December 2024 LMG1025-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
      3. 6.3.3 Bias Supply and Under Voltage Lockout
      4. 6.3.4 Overtemperature Protection (OTP)
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Handling Ground Bounce
        2. 7.2.2.2 Creating Nanosecond Pulse
        3. 7.2.2.3 VDD and Overshoot
        4. 7.2.2.4 Operating at Higher Frequency
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Gate Drive Loop Inductance and Ground Connection
      2. 9.1.2 Bypass Capacitor
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Trademarks
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

LMG1025-Q1 DEE6-Pin WSONTop View Figure 4-1 DEE6-Pin WSONTop View
LMG1025-Q1 DRV6-Pin WSONTop View Figure 4-2 DRV6-Pin WSONTop View
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
GND 2 G Power supply and source return. Connect with a direct path to the transistor’s source.
IN+ 1 I Positive logic-level input.
IN– 6 I Negative logic-level input.
OUTL 5 O Pull-down gate drive output. Connect through an optional resistor to the target transistor’s gate.
OUTH 4 O Pull-up gate drive output. Connect through a resistor to the target transistor’s gate.
VDD 3 P Input voltage supply. Decouple through a compact capacitor to GND.
Thermal Pad - - Internally connected to GND through substrate. Connect this pad to large copper area, generally a ground plane.
(1) I=Input, O=Output, P=Power, G=Ground