SNOSDI8A May   2024  – November 2025 LMG2650

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 LLC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 AHB Application
      3. 8.2.3 Motor Drives Application
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 RFB Package, 19-Pin VQFN (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
NC 1, 6, 9, 11 NC Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The PCB landing pad is non-solder mask defined pad and must not be physically connected to any other metal on the PCB.
INH 2 I High-side gate-drive control input. Referenced to AGND. Signal is level shifted internally to the high-side GaN FET driver. There is a forward biased ESD diode from INH to AUX so avoid driving INH higher than AUX. Short this pin to AGND if GDH pin function is used.
INL 3 I Low-side gate-drive control input. Referenced to AGND. There is a forward biased ESD diode from INL to AUX so avoid driving INL higher than AUX.
CS 4 O Current-sense emulation output. Outputs scaled replica of the GaN FET current. Feed output current into a resistor to create a current sense voltage signal. Reference the resistor to the power supply controller IC local ground. This function replaces the external current sense resistor that is used in series with the low-side FET source.
SL 5, 7 P Low-side GaN FET source. Low-side thermal pad. Internally connected to AGND.
DH 8 P High-side GaN FET drain.
SW 10, 15 P GaN FET half-bridge switch node between the high-side GaN FET source and low-side GaN FET drain. High-side thermal pad.
GDH 12 I High-side gate-drive control input. Referenced to SW. Signal is connected directly to the high-side GaN FET driver. There is a forward biased ESD diode from GDH to BST so avoid driving GDH higher than BST. Short this pin to SW if INH pin function is used.
RDRVH 13 I High-side drive strength control resistor. Set a resistance between RDRVH and SW to program the high-side GaN FET turn-on slew rate.
BST 14 P Bootstrap voltage rail. High-side supply voltage. The bootstrap diode function between AUX and BST is internally provided. Connect an appropriately sized bootstrap capacitor between BST and SW.
RDRVL 16 I Low-side drive strength control resistor. Set a resistance between RDRVL and AGND to program the low-side GaN FET turn-on slew rate.
AGND 17 G Low-side analog ground. Internally connected to SL.
AUX 18 P Auxiliary voltage rail. Low-side supply voltage. Connect a local bypass capacitor between AUX and AGND.
EN 19 I Enable. Used to toggle between active and standby modes. The standby mode has reduced quiescent current to support converter light load efficiency targets. There is a forward biased ESD diode from EN to AUX so avoid driving EN higher than AUX.
(1) I = input, O = output, I/O = input or output, G = ground, P = power, NC = no connect