SNOSDI8B May   2024  – February 2026 LMG2650

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 LLC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 AHB Application
      3. 8.2.3 Motor Drives Application
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics

1) Symbol definitions: VDS(ls) = SW to SL voltage; IDS(ls) = SW to SL current; VDS(hs) = DH to SW voltage; ID(hs) = DH to SW current; ISW = SW point current into device; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; VDS(ls) = 520V; VDS(hs) = 520V; 10V ≤ VAUX ≤ 26V; 7.5V ≤ VBST_SW ≤ 26V; VEN = 5V; VINL = 0V; VINH = 0V; RCS = 100Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW-SIDE GAN POWER FET
td(on)(Idrain)(ls) Drain current turn-on delay time From VINL > VINL,IT+ to ID(ls) > 50mA, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see Section 6.1
slew rate setting 0 (slowest) 48 165 ns
slew rate setting 1 48 100
slew rate setting 2 43 80
slew rate setting 3 (fastest) 34 65
td(on)(ls) Turn-on delay time From VINL > VINL,IT+ to VDS(ls) < 390V, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see Section 6.1
slew rate setting 0 (slowest) 89 255 ns
slew rate setting 1 70 137
slew rate setting 2 59 100
slew rate setting 3 (fastest) 41 75
tr(on)(ls) Turn-on rise time From VDS(ls) < 320V to VDS(ls) < 80V, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see Section 6.1
slew rate setting 0 (slowest) 131 180 ns
slew rate setting 1 51 65
slew rate setting 2 11 19
slew rate setting 3 (fastest) 5 10
td(off)(ls) Turn-off delay time From VINL < VINL,IT– to VDS(ls) > 80V, VBUS = 400V, ISW = 2.65A, (independent of slew rate setting), see Section 6.1 45 65 ns
tf(off)(ls) Turn-off fall time From VDS(ls) > 80V to VDS(ls) > 320V, VBUS = 400V, ISW = 2.65A, (independent of slew rate setting), see Section 6.1 20 ns
Turn-on slew rate From VDS(ls) < 320V to VDS(ls) < 80V, TJ = 25℃, VBUS = 400V, ISW = 2.65A, at following low-side slew rate settings, see Section 6.1
slew rate setting 0 (slowest) 2 V/ns
slew rate setting 1 5
slew rate setting 2 23
slew rate setting 3 (fastest) 50
HIGH-SIDE GAN POWER FET
td(on)(Idrain)(hs,INH) Drain current turn-on delay time From VINH > VINH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 51 160 ns
slew rate setting 1 51 95
slew rate setting 2 45 78
slew rate setting 3 (fastest) 34 62
td(on)(Idrain)(hs,GDH) Drain current turn-on delay time From VGDH > VGDH,IT+ to ID(hs) > 50mA, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 46 150 ns
slew rate setting 1 46 90
slew rate setting 2 41 75
slew rate setting 3 (fastest) 32 63
td(on)(hs,INH) Turn-on delay time From VINH > VINH,IT+ to VDS(hs) < 390V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 75 250 ns
slew rate setting 1 67 133
slew rate setting 2 56 97
slew rate setting 3 (fastest) 39 73
td(on)(hs,GDH) Turn-on delay time From VGDH > VGDH,IT+ to VDS(hs) < 390V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 110 233 ns
slew rate setting 1 83 126
slew rate setting 2 68 96
slew rate setting 3 (fastest) 46 74
tr(on)(hs) Turn-on rise time From VDS(hs) < 320V to VDS(hs) < 80V, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 133 178 ns
slew rate setting 1 50 65
slew rate setting 2 10 18.5
slew rate setting 3 (fastest) 4 10
td(off)(hs,INH) Turn-off delay time From VINH < VINH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 40 55 ns
td(off)(hs,GDH) Turn-off delay time From VGDH < VGDH,IT– to VDS(hs) > 80V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 40 65 ns
tf(off)(hs) Turn-off fall time From VDS(hs) > 80V to VDS(hs) > 320V, VBUS = 400V, ISW = –2.65A, (independent of slew rate setting), see GaN Power FET Switching Parameters 20 ns
Turn-on slew rate From VDS(hs) < 320V to VDS(hs) < 80V, TJ = 25℃, VBUS = 400V, ISW = –2.65A, at following high-side slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 2 V/ns
slew rate setting 1 5
slew rate setting 2 23
slew rate setting 3 (fastest) 50
LOW-SIDE OVERCURRENT PROTECTION
t(OC)(ls) Overcurrent fault response time, FET on before overcurrent From ID(ls) > IT(OC)(ls) to ID(ls) < 0.5 × IT(OC)(ls), ID(ls) di/dt = 125A/µs 75 120 ns
t(OC)(en)(ls) Overcurrent fault response time, FET enabled into a short VDS(ls) = 100V; From ID(ls) > IT(OC)(ls) to ID(ls) < 0.5 × IT(OC)(ls), at following slew rate setting
slew rate setting 0 (slowest) 390 470 ns
slew rate setting 1 205 235 ns
slew rate setting 2 175 205 ns
slew rate setting 3 (fastest) 125 172 ns
HIGH-SIDE OVERCURRENT PROTECTION
t(OC)(hs) Overcurrent fault response time, FET on before overcurrent From ID(ls) > IT(OC)(ls) to ID(ls) < 0.5 × IT(OC)(ls), ID(hs) di/dt = 125A/µs 65
125

 ns
t(OC)(en)(hs) Overcurrent fault response time, FET enabled into a short VDS(hs) = 100V; From ID(hs) > IT(OC)(hs) to ID(hs) < 0.5 × IT(OC)(hs), at following slew rate setting
slew rate setting 0 (slowest) 330 375 ns
slew rate setting 1 175 190 ns
slew rate setting 2 145 170 ns
slew rate setting 3 (fastest) 100 150 ns
CS
tr Rise time From ICS(src) > 0.2 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0V ≤ VCS ≤ 2V, Low-side enabled into a 2.65A load 30 ns
EN, INL, INH
EN wake-up time From VEN > VIT+ to ID(ls) > 10mA, VINL = 5V 1.5 µs
Minimum INL L-H-L pulse that changes the low-side output VINL 0V to 5V to 0V at 5V/ns, VDS(ls) has to fall to 200 V, VBUS = 400V, ISW = 2.5A, at below low-side slew rate settings
slew rate setting 0 (slowest) 190 ns
slew rate setting 1 100
slew rate setting 2 55
slew rate setting 3 (fastest) 25
Minimum INH L-H-L pulse that changes the high-side output VINH 0V to 5V to 0V at 5V/ns, VDS(hs) has to fall to 200V, VBUS = 400V, ISW = –2.5A, at below high-side slew rate settings
slew rate setting 0 (slowest) 210 ns
slew rate setting 1 95
slew rate setting 2 65
slew rate setting 3 (fastest) 30
BST
Start-up time from deep BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH or GDH high level with VBST_SW rising from 0V to 10V in 1µs 5 µs
Start-up time from shallow BST to SW discharge From VBST_SW > VBST_SW,T+(UVLO) to high-side reacts to INH or GDH high level with VBST_SW rising from 5V to 10V in 0.5µs 3.2 µs