SNOSDL1A December   2024  – December 2025 LMG3650R035

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On and Turn-off Slew Rate
      4. 6.1.4 Zero-Voltage Detection Times (LMG3656R035 only)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3650R035 Functional Block Diagram
      2. 7.2.2 LMG3651R035 Functional Block Diagram
      3. 7.2.3 LMG3656R035 Functional Block Diagram
      4. 7.2.4 LMG3657R035 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drive Strength Adjustment
      2. 7.3.2 GaN Power FET Switching Capability
      3. 7.3.3 VDD Supply
      4. 7.3.4 Overcurrent and Short-Circuit Protection
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Fault Reporting
      8. 7.3.8 Auxiliary LDO (LMG3651R035 Only)
      9. 7.3.9 Zero-Voltage Detection (ZVD) (LMG3656R035 Only)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Slew Rate Selection
        2. 8.2.1.2 Signal Level-Shifting
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Using an Isolated Power Supply
      2. 8.3.2 Using a Bootstrap Diode
        1. 8.3.2.1 Diode Selection
        2. 8.3.2.2 Managing the Bootstrap Voltage
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Reliability
        2. 8.4.1.2 Power-Loop Inductance
        3. 8.4.1.3 Signal-Ground Connection
        4. 8.4.1.4 Bypass Capacitors
        5. 8.4.1.5 Switch-Node Capacitance
        6. 8.4.1.6 Signal Integrity
        7. 8.4.1.7 High-Voltage Spacing
        8. 8.4.1.8 Thermal Recommendations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information
    3.     70

8.4.2 Layout Example

Correct layout of the LMG365xR035 and surrounding components is essential for correct operation. The layouts shown here reflect the GaN device schematic in Figure 8-1. The layouts in Figure 8-1 produce good results and are intended as a guideline. However, obtaining acceptable performance with alternate layout schemes is possible. Additionally, please refer to the land pattern example in Section 11.2 for the latest recommended PCB footprint of the device.

The top-layer layout and mid-layer layout are shown. The layouts are zoomed in to the LMG3650R035 U2 and U4 component placements. The mid-layer layout includes the outlines of the top layer components to assist the user in lining up the top-layer and mid-layer layouts.

LMG3650R035 LMG3651R035 LMG3656R035 LMG3657R035 LMG3650R035 Half-Bridge Top-Layer Layout Figure 8-12 LMG3650R035 Half-Bridge Top-Layer Layout
LMG3650R035 LMG3651R035 LMG3656R035 LMG3657R035 LMG3650R035 Half-Bridge Mid-Layer Layout Figure 8-13 LMG3650R035 Half-Bridge Mid-Layer Layout