SNVAA25A January   2022  – July 2022 DP83TD510E , ESDS302 , LM5155 , LM66100 , MSP430FR2476 , TL431LI , TLV3012

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 10BASE-T1L (IEEE 802.3cg) PoDL Overview
    2. 1.2 PoDL PSE Types and Power Classes
  4. 2Terminology
  5. 3PD Design
    1. 3.1 PD Design Overview
    2. 3.2 Coupling and Decoupling Network (CDN)
    3. 3.3 VID Circuit
    4. 3.4 SCCP Communication
    5. 3.5 Protection Features
    6. 3.6 Power and Scalability
  6. 4References
  7. 5Revision History

10BASE-T1L (IEEE 802.3cg) PoDL Overview

The IEEE Std 802.3cg-2019 Ethernet physical layer standard was released by the IEEE on November 7, 2019. The standard brings a new standardized option for long-distance communication over only a single balanced twisted conductor pair up to 1000 m in length. The standard allows engineers to use their existing hardware and software knowledge of Ethernet networks to bring the existing complex communication infrastructure under the familiar Ethernet family of networking technologies. The new approach also allows for seamless connectivity of actuators, sensors, and other equipment, thereby improving operational efficiency especially in the building and factory automation markets. This converges potentially fragmented networks.

The 10BASE-T1L Ethernet variant in the IEEE 802.3cg standard defines a 10 Mbps, full duplex, point-to-point communication scheme. The DP83TD510E Ethernet PHY fully supports this new standard and goes beyond the specification by supporting lengths up to 2000 meters, providing design flexibility and maximizing cable reach over a single balanced pair of conductors.

The IEEE 802.3cg standard extends the PoDL section of theIEEE 802.3bu standard adding support for longer distance cable reach and additional power classes. The replacement of 4 mA to 20 mA or field bus communications in many cases reduces design complexity, eliminates power hungry gateways, and increases the available power to connected equipment. This is in addition to signficant faster data rate compared to 4-20 mA current loops, as well as the addition of a back channel. Also in comparison to other protocols, HART allows a back channel, but is relatively slow (1200 bps). IO-Link is faster than HART (up to 230 kbps), but is limited to 20 m.

Figure 1-1 illustrates a high-level diagram of PoDL. The implementation of PoDL requires the design of a compliant Power Sourcing Equipment (PSE), a Powered Device (PD) as well as the link segment between the two. The PSE supplies power to the link and the PD draws power from that link.


GUID-20210908-SS0I-3TFF-9FCB-RWG1TTX3CM03-low.gif

Figure 1-1 Power Over Data Lines (PoDL) High-Level Diagram