SNVSB03E December   2018  – May 2026 TPS3840

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Transient Immunity
      2. 7.3.2 User-Programmable Reset Time Delay
      3. 7.3.3 Manual Reset (MR) Input
      4. 7.3.4 Output Logic
        1. 7.3.4.1 RESET Output, Active-Low
        2. 7.3.4.2 RESET Output, Active-High
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 VDD Between VPOR and VDD(min)
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 Application Curve: TPS3840EVM
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

At 1.5V ≤ VDD ≤ 10V, CT = MR = Open, RESET pull-up resistor (Rpull-up) = 100kΩ to VDD, output reset load (CLOAD) = 10pF and over the operating free-air temperature range – 40°C to 125°C, VDD slew rate < 100mV / us, unless otherwise noted. Typical values are at TJ = 25°C. 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup Delay(1) CT pin open 100 220 350 µs
tP_HL Propagation detect delay for VDD falling below VIT- VDD = VIT+ to (VIT-) - 10%(2) 15 30 µs
tD Reset time delay(3) CT pin = open
 		 50 µs
CT pin = 10nF 6.2 ms
CT pin = 1 µF 619 ms
tGI_VIT- Glitch immunity VIT- 5% VIT- overdrive(4) 10 µs
tMR_PW MR pin pulse duration to initiate reset 300 ns
tMR_RES Propagation delay from MR low to reset VDD = 4.5V, MR < VMR_L 700 ns
tMR_tD Delay from release MR to deasert reset VDD = 4.5V,
MR = VMR_L to VMR_H  		 tD ms
(1) When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is release after the startup delay (tSTRT), a capacitor at CT pin adds tD delay to tSTRT time
(2) tP_HL measured from the threshold trip point (VIT-) to VOL for active low variants and VOH for active high variants. 
(3) The MIN and MAX reset time delay with external capacitor depends on RCT and is calculated using Equation 5 and Equation 6 in Section 7.3.2
(4)
Equation 1. O v e r d r i v e % = V D D V I T - - 1 × 100 %
TPS3840 Timing Diagram TPS3840DL (Open-Drain Active-Low)
A. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time is added to the startup time, VDD slew rate = 100mV/µs.
B. Open-Drain timing diagram assumes pull-up resistor is connected to RESET
C. RESET output is undefined when VDD is < VPOR
Figure 6-1 Timing Diagram TPS3840DL (Open-Drain Active-Low)
TPS3840 Timing Diagram TPS3840PL (Push-Pull Active-Low)
A. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time is added to the startup time. VDD slew rate = 100mV/µs.
B. RESET output is undefined when VDD < VPOR and limited to VOL for VDD slew rate = 100mV/µs
Figure 6-2 Timing Diagram TPS3840PL (Push-Pull Active-Low)
TPS3840 Timing Diagram TPS3840PH (Push-Pull Active-High)
A. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin, then tD programmed time is added to the total startup time. VDD slew rate = 100mV/µs.
Figure 6-3 Timing Diagram TPS3840PH (Push-Pull Active-High)