SNVSB03E December   2018  – May 2026 TPS3840

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Transient Immunity
      2. 7.3.2 User-Programmable Reset Time Delay
      3. 7.3.3 Manual Reset (MR) Input
      4. 7.3.4 Output Logic
        1. 7.3.4.1 RESET Output, Active-Low
        2. 7.3.4.2 RESET Output, Active-High
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 VDD Between VPOR and VDD(min)
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 Application Curve: TPS3840EVM
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.3.2 Detailed Design Procedure

The primary constraint for this application is monitoring a 12V rail while preventing the VDD pin on TPS3840 from exceeding the recommended maximum of 10V. This is accomplished by sizing the resistor divider so that when the 12V rail drops to 10V, the VDD pin for TPS3840 is at 4.9V which is the VIT- threshold for triggering a undervoltage condition for TPS3840DL49 as shown in Equation 8.

Equation 8. V r a i l _ t r i g g e r = V I T - × R t o p + R b o t t o m ÷ R b o t t o m

where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of TPS3840, and Rtop and Rbottom are the top and bottom resistors of the external resistor divider. Be sure to size the resistor values such that the current through the external resistor divider is much greater than IDD to preserve voltage monitoring accuracy. VIT- is fixed per device variant and is 4.9V for TPS3840DL49. Substituting in the values from Figure 8-5, the undervoltage trigger threshold for the rail is set to 10.045V.

Since the undervoltage trigger of 10V on the rail corresponds to 4.9V undervoltage threshold trigger of the TPS3840 device, there is plenty of room for the rail to rise up while maintaining less than 10V on the VDD pin of the TPS3840. Equation 9 shows the maximum rail voltage that still meets the 10V maximum at the VDD pin for TPS3840.

Equation 9. V r a i l _ m a x = 10 × 10500 + 10000 ÷ 10000 = 20.5 V

This means the monitored voltage rail can go as high as 20.5V and still not violate the recommended maximum for the VDD pin on TPS3840. This is useful when monitoring a voltage rail that has a wide range that can go much higher than the nominal rail voltage such as in this case with the specification that the 12V rail can go as high as 18V. Notice that the resistor values selected are less than 100kΩ to preserve the accuracy set by the internal resistor divider. Good design practice recommends using a 0.1µF capacitor on the VDD pin and this capacitance can require an increase when using an external resistor divider.