SNVSB03E December   2018  – May 2026 TPS3840

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Transient Immunity
      2. 7.3.2 User-Programmable Reset Time Delay
      3. 7.3.3 Manual Reset (MR) Input
      4. 7.3.4 Output Logic
        1. 7.3.4.1 RESET Output, Active-Low
        2. 7.3.4.2 RESET Output, Active-High
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 VDD Between VPOR and VDD(min)
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 Application Curve: TPS3840EVM
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.1.2 Detailed Design Procedure

The primary constraint for this application is selecting the correct device to monitor the supply voltage of the microprocessor. The TPS3840 can monitor any voltage from 1.6V to 10V and is available in 0.1V increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to select. In this example, the first TPS3840 triggers when the 3.3V rail falls to 3.0V. The second TPS3840 triggers a reset when the 1.8V rail falls to 1.6V. The secondary constraint for this application is the reset time delay that must be at least 25ms to allow the microprocessor, and all other devices using the 3.3V rail, enough time to startup correctly before the 1.8V rail is enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For applications with ambient temperatures ranging from –40°C to +125°C, CCT can be calculated using RCT and solving for CCT in Equation 3. Solving Equation 3 for 25ms gives a minimum capacitor value of 0.04 µF which is rounded up to a standard value 0.047µF to account for capacitor tolerance.

A 1µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5mA limit found in the Section 6.3: RPull-up = VPull-up ÷ 5mA. For this design, a standard 10kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the pull-up resistor, the higher VOL. The MR pin can be connected to an external signal if desired or left floating if not used due to the internal pull-up resistor to VDD.