SNVSC27B October   2022  – January 2025 TPS38700

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device State Diagram
      2. 7.3.2 Built-In Self Test and Configuration Load
      3. 7.3.3 CLK32K
      4. 7.3.4 BACKUP State
      5. 7.3.5 FAILSAFE State
      6. 7.3.6 Transitioning Sequences
        1. 7.3.6.1 Sequence 1: Power Up
        2. 7.3.6.2 Sequence 2: Emergency Power Down
        3. 7.3.6.3 Sequence 3: Sleep Entry
        4. 7.3.6.4 Sequence 4: Sleep Exit
        5. 7.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 7.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 7.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 7.3.6.8 Sequence 9: Failsafe Power Down
        9. 7.3.6.9 Output Sequencing
      7. 7.3.7 I2C
        1. 7.3.7.1 Packet Error Checking (PEC)
    4. 7.4 Register Map Table
      1. 7.4.1 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Automotive Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12.   Mechanical, Packaging, and Orderable Information

9.1 Device Nomenclature

Table 9-1 shows how to decode the function of the device based on the device ordering code, while
Table 9-2 shows the sequence configuration based on the device ordering code. See Figure 4-1 for more information regarding how to decode the device part number.

Table 9-1 Device Comparison Table
ORDERING CODEFUNCTIONSEN PINS DEFAULTALT FUNC. PINSTIME SLOT (μsec)I2C ADDR.RESET DELAY (msec)WATCHDOGPEC(1)I2C PULL-UP VOLTAGE (V)
TPS38700C04NRGERSequencer, NEM_PDPush-Pull LowOpen-Drain6253C16DisabledEnabled3.3
TPS38700801NRGER Sequencer Push-Pull Low N/A 10500 3C 16 Disabled Disabled 1.2
TPS38700B01NRGER Sequencer Push-Pull Low N/A 10500 3C 16 Disabled Disabled 1.2
(1) For parts with PEC enabled:
  1. PEC calculation is based on initializing to 0x00.
  2. In case of a PEC violation there needs to be a subsequent I2C transaction before NIRQ is asserted.
  3. If incorrect PEC is given NIRQ is asserted.
  4. If there is an extra byte after successfully writing the correct PEC byte, NIRQ is asserted and the write fails.
Table 9-2 Sequence Configuration Table
ORDERING CODEPINSSEQUENCE UPSEQUENCE DOWN
04NPWR_EN1Power Up Slot 1Power Down Slot 5
PWR_EN2Power Up Slot 1Power Down Slot 1
PWR_EN3Power Up Slot 2Power Down Slot 4
PWR_EN4Power Up Slot 2Power Down Slot 4
PWR_EN5Power Up Slot 4Power Down Slot 2
PWR_EN6Power Up Slot 6Power Down Slot 1
PWR_EN7Power Up Slot 1Power Down Slot 1
PWR_EN8Power Up Slot 2Power Down Slot 4
PWR_EN9Power Up Slot 4Power Down Slot 2
PWR_EN10Power Up Slot 0Power Down Slot 0
PWR_EN11Power Up Slot 4Power Down Slot 2
PWR_EN12Power Up Slot 0Power Down Slot 0
PWR_CLK32Power Up Slot 4Power Down Slot 4
Sequence DownSequence Up
SLP_EN1Sleep Exit Slot 0Sleep Entry Slot 0
SLP_EN2Sleep Exit Slot 1Sleep Entry Slot 3
SLP_EN3Sleep Exit Slot 3Sleep Entry Slot 2
SLP_EN4Sleep Exit Slot 0Sleep Entry Slot 0
SLP_EN5Sleep Exit Slot 0Sleep Entry Slot 0
SLP_EN6Sleep Exit Slot 2Sleep Entry Slot 1
SLP_EN7Sleep Exit Slot 1Sleep Entry Slot 3
SLP_EN8Sleep Exit Slot 3Sleep Entry Slot 2
SLP_EN9Sleep Exit Slot 4Sleep Entry Slot 1
SLP_EN10Sleep Exit Slot 0Sleep Entry Slot 0
SLP_EN11Sleep Exit Slot 1Sleep Entry Slot 1
SLP_EN12Sleep Exit Slot 0Sleep Entry Slot 0
SLP_CLK32Sleep Exit Slot 0Sleep Entry Slot 0
Table 9-3 Sequence Configuration Table
ORDERING CODE PINS SEQUENCE UP SEQUENCE DOWN
801N PWR_EN1 Power Up Slot 5 Power Down Slot 4
PWR_EN2 Power Up Slot 3 Power Down Slot 6
PWR_EN3 Power Up Slot 1 Power Down Slot 8
PWR_EN4 Power Up Slot 6 Power Down Slot 3
PWR_EN5 Power Up Slot 8 Power Down Slot 1
PWR_EN6 Power Up Slot 7 Power Down Slot 2
PWR_EN7 Power Up Slot 4 Power Down Slot 5
PWR_EN8 Power Up Slot 2 Power Down Slot 7
Table 9-4 Sequence Configuration Table
ORDERING CODE PINS SEQUENCE UP SEQUENCE DOWN
B01N PWR_EN1 Power Up Slot 1 Power Down Slot 1
PWR_EN2 Power Up Slot 2 Power Down Slot 2
PWR_EN3 Power Up Slot 2 Power Down Slot 2
PWR_EN4 Power Up Slot 3 Power Down Slot 3
PWR_EN5 Power Up Slot 3 Power Down Slot 3
PWR_EN6 Power Up Slot 4 Power Down Slot 4
PWR_EN7 Power Up Slot 4 Power Down Slot 4
PWR_EN8 Power Up Slot 4 Power Down Slot 4
PWR_EN9 Power Up Slot 4 Power Down Slot 4
PWR_EN10 Power Up Slot 5 Power Down Slot 5
PWR_EN11 Power Up Slot 5 Power Down Slot 5