SNVSC27 Data sheet

SNVSC27B October 2022 – January 2025 TPS38700

PRODUCTION DATA

6.6 Timing Requirements

At 2V ≤ VDD ≤ 5.5V, NIRQ/NRST Voltage = 10kΩ to VDD, NIRQ/NRST load = 10pF, and over the operating free-air temperature range of – 40°C to 125°C, unless otherwise noted. Typical values are at T_A = 25°C, typical conditions at VDD = 3.3V.

			MIN	NOM	MAX	UNIT
Common parameters
t_{D_ENx}	ENx toggle delay from start of time slot	From start of time slot			10	µs
t_{D_CLK32K}	CLK32K toggle delay from start of time slot	From start of time slot			10	µs
F_CLK32K	Frequency	Capacitive load = 12pF		32768		Hz
D_CLK32K	Duty cycle	Capacitive load = 12pF	40	50	60	%
Trf_CLK32K	Rise and fall time of CLK32K (Rpullup = 4.7kΩ)	Capacitive load = 12pF			50	ns
t_{D_ENx,y}	Delay between 2 subsequent EN in same time slot				1	µs
t_{NRST_EN}	ENx delay from NRST in Emergency Shutdown	Sequence 2 and 9	200			ns
t_{D_NRST}	NRST assertion latency from falling edge of ACT pin below VIL or falling edge of VDD pin below VDD_min				25	µs
t_{D_NIRQ}	Fault detection to NIRQ assertion latency				25	µs
t_BIST	POR to ready with BIST	including OTP load with ECC			15	ms
t_{No_BIST}	POR to ready without BIST	including OTP load with ECC			2.5	ms
BIST time					12.5	ms
t_{Startup_CLK32K}	Clock 32k startup from UVLO at power ON				50	ms
Freq_fault	Crystal frequency fault detection time				1	ms
I2C Timing Characteristics
f_SCL	Serial clock frequency ⁽¹⁾	Standard mode			100	kHz
f_SCL	Serial clock frequency ⁽¹⁾	Fast mode			400	kHz
f_SCL	Serial clock frequency ⁽¹⁾	Fast mode +			1	MHz
t_LOW	SCL low time ⁽¹⁾	Standard mode	4.7			µs
t_LOW	SCL low time ⁽¹⁾	Fast mode	1.3			µs
t_LOW	SCL low time ⁽¹⁾	Fast mode +	0.5			µs
t_HIGH	SCL high time ⁽¹⁾	Standard mode	4			µs
t_HIGH	SCL high time ⁽¹⁾	Fast Mode	1			µs
t_HIGH	SCL high time ⁽¹⁾	Fast mode +	0.26			µs
t_{SU_DAT}	Data setup time ⁽¹⁾	Standard mode	250			ns
t_{SU_DAT}	Data setup time ⁽¹⁾	Fast mode	100			ns
t_{SU_DAT}	Data setup time ⁽¹⁾	Fast mode +	50			ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Standard mode	10		3450	ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Fast mode	10		900	ns
t_{HD_DAT}	Data hold time ⁽¹⁾	Fast mode +	10			ns
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Standard mode	4.7			µs
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Fast mode	0.6			µs
t_{SU_STA}	Setup time for a Start or Repeated Start condition ⁽¹⁾	Fast mode +	0.26			µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Standard mode	4			µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Fast mode	0.6			µs
t_{HD_STA}	Hold time for a Start or Repeated Start condition ⁽¹⁾	Fast mode +	0.26			µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Standard mode	4.7			µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Fast mode	1.3			µs
t_BUF	Bus free time between a STOP and START condition ⁽¹⁾	Fast mode +	0.5			µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Standard mode	4			µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Fast mode	0.6			µs
t_{SU_STO}	Setup time for a Stop condition ⁽¹⁾	Fast mode +	0.26			µs
t_rDA	Rise time of SDA signal ⁽¹⁾	Standard mode			1000
t_rDA	Rise time of SDA signal ⁽¹⁾	Fast mode	20		300	ns
t_rDA	Rise time of SDA signal ⁽¹⁾	Fast mode +			120	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Standard mode			300	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Fast mode	1.4		300	ns
t_fDA	Fall time of SDA signal ⁽¹⁾	Fast mode +	6.5		120	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Standard mode			1000	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Fast mode	20		300	ns
t_rCL	Rise time of SCL signal ⁽¹⁾	Fast mode +			120	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Standard mode			300	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Fast mode	6.5		300	ns
t_fCL	Fall time of SCL signal ⁽¹⁾	Fast mode +	6.5		120	ns
t_SP	Pulse width of SCL and SDA spikes that are suppressed ⁽¹⁾	Standard mode, Fast mode and Fast mode +			50	ns

(1) Characterized by design