SNVSCE6B October   2023  – February 2026 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
    1. 4.1 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latch
        4. 7.3.3.4 UVBypass
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: Off-Battery Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4 Device Functional Modes

Table 7-4 Undervoltage Detect Functional Mode Truth Table
DESCRIPTIONSENSECTR (1)VDD PINOUTPUT (2)
(RESET PIN)
PREVIOUS CONDITIONCURRENT CONDITION
Normal OperationSENSE > VITNSENSE > VITNOpen or capacitor connectedVDD > VDD(MIN)High
Undervoltage DetectionSENSE > VITNSENSE < VITNOpen or capacitor connectedVDD > VDD(MIN)Low
Undervoltage DetectionSENSE < VITNVITN < SENSE < VITN + HYSOpen or capacitor connectedVDD > VDD(MIN)Low
Normal OperationSENSE < VITNSENSE > VITN + HYSOpen or capacitor connectedVDD > VDD(MIN)High
UVLO EngagedSENSE > VITNSENSE > VITNOpen or capacitor connectedVPOR < VDD < VDD(MIN)Low
Below VPOR, Undefined OutputSENSE > VITNSENSE > VITNOpen or capacitor connectedVDD < VPORUndefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pullup resistor to a pull-up voltage.
Table 7-5 Overvoltage Detect Functional Mode Truth Table
DESCRIPTIONSENSECTR (1)VDD PINOUTPUT (2)
(RESET PIN)
PREVIOUS CONDITIONCURRENT CONDITION
Normal OperationSENSE < VITPSENSE < VITPOpen or capacitor connectedVDD > VDD(MIN)High
Overvoltage DetectionSENSE < VITPSENSE > VITPOpen or capacitor connectedVDD > VDD(MIN)Low
Overvoltage DetectionSENSE > VITPVITP - HYS < SENSE < VITPOpen or capacitor connectedVDD > VDD(MIN)Low
Normal OperationSENSE > VITPSENSE < VITP - HYSOpen or capacitor connectedVDD > VDD(MIN)High
UVLO EngagedSENSE < VITPSENSE < VITPOpen or capacitor connectedVPOR < VDD < UVLOLow
Below VPOR, Undefined OutputSENSE < VITPSENSE < VITPOpen or capacitor connectedVDD < VPORUndefined
(1) Reset time delay is ignored in the truth table.
(2) Open-drain active low output requires an external pullup resistor to a pull-up voltage.