SNVSCE6B October   2023  – February 2026 TPS3762-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
    1. 4.1 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Reverse Polarity Protection
        2. 7.3.2.2 SENSE Hysteresis
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (RESET)
        3. 7.3.3.3 Latch
        4. 7.3.3.4 UVBypass
      4. 7.3.4 User-Programmable Reset Time Delay
        1. 7.3.4.1 Reset Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Adjustable Voltage Thresholds
    3. 8.3 Typical Application
      1. 8.3.1 Design 1: Off-Battery Monitoring
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Setting Voltage Threshold
          2. 8.3.1.2.2 Meeting the Sense and Reset Delay
          3. 8.3.1.2.3 Setting Supply Voltage
          4. 8.3.1.2.4 Initiating Built-In Self-Test and Clearing Latch
        3. 8.3.1.3 Application Curves
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Dissipation and Device Operation
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.5.1 Sense Time Delay Configuration

SENSE time delay (tCTS) occurs when the RESET is transitioning from a non-fault state (VOH) to a fault state (VOL). The time delay (tCTS) can be programmed by connecting a capacitor between CTS pin and GND.

The relationship between external capacitor CCTS_EXT (typ) in μF and the time delay tCTS (typ) in seconds is given by Equation 4.

Equation 4. tCTS (typ) = 3.7 × CCTS_EXT (typ) +0.000085

CCTS_EXT (typ) = is given in microfarads (μF)

tCTS (typ) = is given in seconds (s)

The sense delay varies according to three variables: the external capacitor (CCTS_EXT), CTS pin internal resistance (RCTS) provided in Section 6.5, and the constant ( tCTS (no cap)) provided in Section 6.6. The minimum and maximum variance due to the constant is show in Equation 5 and Equation 6:

Equation 5. tCTS (min) = 2.96 × CCTS_EXT (min)
Equation 6. tCTR (max) = 4.44 × CCTS_EXT (max) + 0.0001

The recommended maximum sense delay capacitor for the TPS3762-Q1 is 10μF as this makes sure there is enough time for the capacitor to fully discharge when a voltage fault occurs. Also, having a too large of a capacitor value can cause very slow charge up (rise times) and system noise can cause the internal circuit to trip unpredictably. This leads to a variation in time delay where the delay accuracy can be worse in the presence of system noise.

* Leakages on the capacitor can effect accuracy of sense time delay.

Table 7-3 Reset Sense Delay for Common Ideal Capacitor Values

CCTS_EXT

 SENSE TIME DELAY (tCTS)

UNIT

MIN

(1)

TYP

MAX

(1)

33nF

 97.68

122.185

146.62

ms

100nF

296

370.085

444.1

ms

1µF

2960

3700.085

4440.1

ms
(1) Minimum and maximum values are calculated using ideal capacitors.