SNVSCN3A April   2025  – May 2026 TPS371K-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 SENSE Hysteresis
      3. 7.3.3 Adjustable Voltage Thresholds
      4. 7.3.4 Release Time Delay
        1. 7.3.4.1 Capacitor Adjustable Release Time Delay Configuration
      5. 7.3.5 Sense Time Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test (BIST)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: DC-Link Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting Voltage Threshold
          2. 8.2.1.2.2 Meeting the Sense and Reset Delay
          3. 8.2.1.2.3 Setting Supply Voltage
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TPS371K-Q1 DFX Package,15-Pin SOIC,TPS371KA-Q1 Adjustable Version (Top View)Figure 5-1 DFX Package,
15-Pin SOIC,
TPS371KA-Q1 Adjustable Version (Top View)
TPS371K-Q1 DFX Package,15-Pin SOIC,TPS371K-Q1 Fixed Version (Top View)Figure 5-3 DFX Package,
15-Pin SOIC,
TPS371K-Q1 Fixed Version (Top View)
TPS371K-Q1 DFX Package,15-Pin SOIC,TPS371KB-Q1 Adjustable Version (Top View)Figure 5-2 DFX Package,
15-Pin SOIC,
TPS371KB-Q1 Adjustable Version (Top View)
Table 5-1 Pinout Table
OPN PinoutPin 8****Pin 10 ***Pin 13 **Pin 14 *
ABIST ENBISTOUT UVOUT OV
BNCNCOUT UVOUT OV
CBIST ENLOW UV & BISTOUT UVOUT OV
DNCLOW UVOUT UVOUT OV
EBIST ENBISTLOW UVOUT OV
FNCNCLOW UVOUT OV
Table 5-2 Pin Functions
PINI/ODESCRIPTION
NAMETPS371KANO.TPS371KBNO.TPS371K Fixed NO.
SENSE111ISense Voltage: Connect this pin to the voltage rail that must be monitored.
GND4, 74, 74,5,6,9-Ground. All GND pins must be electrically connected to the board ground.
CTR5

5

10

ORelease Time Delay: User-programmable release time delay for output pins. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

See Device Nomenclature table for output pin configurations.

CTS6611OSENSE Time Delay: User-programmable sense time delay for SENSE. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

See Device Nomenclature table for output pin configurations.

VSENSE9--OVoltage SENSE: The output of the integrated buffer that is a scaled down voltage of the SENSE pin.

See Device Nomenclature table for output pin configurations.

ADJ UV1111-I

Adjustable Undervoltage Threshold: User can program the internal undervoltage thresholds by using external resistors to set a voltage at start-up.

See voltage threshold table for selectable threshold options.

ADJ OV1212-IAdjustable Overvoltage Threshold: User can program the internal overvoltage threshold by using external resistors to set a voltage at start-up.

See voltage threshold table for selectable threshold options.

OUT UVSee Pinout TableSee Pinout Table7OOutput Undervoltage Signal: OUT UV asserts when SENSE crosses the undervoltage threshold. Assertion time delay is either fixed or set by CTS. OUT UV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor.

See Device Nomenclature table for OUT UV threshold and timing configurations.

Output topology: Open-Drain Active-Low

OUT OVSee Pinout TableSee Pinout Table14OOutput Overvoltage Signal: OUT OV asserts when SENSE crosses the Overvoltage threshold. Assertion time delay is either fixed or set by CTS. OUT OV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor.

See Device Nomenclature table for OUT OV threshold and timing configurations.

Output topology: Open-Drain Active-Low

LOW UVSee Pinout TableSee Pinout Table-OOutput Low Undervoltage Signal: OUT Low UV asserts when SENSE crosses the Low Overvoltage threshold after the sense time delay, set by CTS. OUT Low UV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor.

Output topology: Open-Drain Active-Low

BISTSee Pinout TableSee Pinout Table-OOutput Built-in Self-test (BIST): BIST asserts when BIST is in operation. BIST operation is initiated at device start-up and by a rising edge on BIST_EN pin. BIST is a device diagnostic test that checks for internal failures. If there is a failure, BIST stays asserted. Upon successful BIST, BIST pin de-asserts.

Output topology: Open-Drain Active-Low

BIST_ENSee Pinout TableSee Pinout Table-IBuilt-in Self-test Enable (BIST EN): A rising edge on BIST enable pin initiates the BIST. For variants with latch, BIST EN also enables and disables latch.
VDD151515IInput Supply Voltage: Supply voltage pin. Bypass with a 0.1µF capacitor to GND for noisy environments.
NC2, 3, 82, 3, 82, 4, 8, 12-No Connect: Leave pins floating or connect to GND.
DNC-713-Do Not Connect: Leave pins floating for proper operation.