SNVSCN3A April   2025  – May 2026 TPS371K-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 SENSE Hysteresis
      3. 7.3.3 Adjustable Voltage Thresholds
      4. 7.3.4 Release Time Delay
        1. 7.3.4.1 Capacitor Adjustable Release Time Delay Configuration
      5. 7.3.5 Sense Time Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Built-In Self-Test (BIST)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: DC-Link Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting Voltage Threshold
          2. 8.2.1.2.2 Meeting the Sense and Reset Delay
          3. 8.2.1.2.3 Setting Supply Voltage
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.2 Layout Example

The layout example in Figure 8-3 shows how the TPS371K-Q1 is laid out on a printed circuit board (PCB) with user-defined delays.

TPS371K-Q1 TPS371K-Q1 Recommended LayoutFigure 8-3 TPS371K-Q1 Recommended Layout