The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum of 4.7µF of ceramic capacitance is required on the input of the LM63635C-Q1, connected directly between VIN and PGND. This must be rated for at least the maximum input voltage that the application requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. More input capacitance is required for larger output currents. In addition, a small case size, 220nF ceramic capacitor must be used at the input as close a possible to the regulator, typically within 1mm of the VIN and PGND pins. This placement provides a high frequency bypass for the control circuits internal to the device. For this example, a 10µF, 50V, X7R (or better) ceramic capacitor is chosen. Two 4.7µF capacitors can also be used. The 220nF must also be rated at 50V with an X7R dielectric and preferably a small case size, such as an 0603.

Many times, Using an electrolytic capacitor on the input in parallel with the ceramics is desirable. This statement is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. Use Equation 8 to calculate the approximate RMS current. Check this value against the manufacturer maximum ratings.

The input capacitor is part of the buck converter high di/dt current loop. The high di/dt current, together with excessive parasitic inductance between the IC and the input capacitor, can result in excessive voltage ringing on the SW node of the IC. The placement of the input capacitor on the board is critical for minimizing the parasitic inductance in the high di/dt loop and accordingly minimizing the SW node ringing at each switching.

For designs targeting the maximum operating voltage of the regulator, make sure that the ringing on the SW node must not exceed the absolute maximum rating of the device. The SW node ringing is a function of how well the input capacitor is positioned with respect to the IC. Refer to the PCB layout examples in Layout Example for proper placement of the input capacitors.