SNVSCP5C April   2025  – August 2026 TPS7H3024-SP , TPS7H3034-SP , TPS7H3124-SP , TPS7H3134-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Quality Conformance Inspection
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (IN), VLDO, and REFCAP
        1. 8.3.1.1 Undervoltage Lockout (VPOR_IN < VIN < UVLO)
        2. 8.3.1.2 Power-On Reset (VIN < VPOR_IN)
      2. 8.3.2 SR_UVLO
      3. 8.3.3 SENSEx Inputs
        1. 8.3.3.1 VTH_SENSEX and VOUTx_RISE
        2. 8.3.3.2 IHYS_SENSEx and VOUTx_FALL
        3. 8.3.3.3 Input to Output Time Diagrams
        4. 8.3.3.4 Top and Bottom Resistive Divider Design Equations
      4. 8.3.4 MODE
      5. 8.3.5 Output Stages (RESETx, PWRGD, WDO, PULL_UP1, and PULL_UP2)
        1. 8.3.5.1 Push-Pull Outputs
        2. 8.3.5.2 Open-Drain Outputs (TPS7H3124 and TPS7H3134)
      6. 8.3.6 WDI
      7. 8.3.7 User-Programmable TIMERS
        1. 8.3.7.1 DLY_TMR
        2. 8.3.7.2 WD_TMR
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Window Voltage Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Power Supplies and Decoupling Capacitors
          2. 9.2.1.2.2 SR_UVLO Threshold
          3. 9.2.1.2.3 SENSEx Thresholds
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Supervision of Negative Voltage Rails
        1. 9.2.2.1 Negative Voltage Monitoring Example
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.1 Input Voltage (IN), VLDO, and REFCAP

During steady state operation, the input voltage of the TPS7H3024 must be from 3V to 14V. A minimum bypass capacitance of 0.1μF is required between VIN and GND. The input bypass capacitors is recommended to be placed as close to the device as possible. The VIN slew rate must be controlled between 10V/μs to 1mV/μs for proper IC operation.

The voltage applied at VIN serves as the input for the internal regulator that generates the VLDO voltage, typically 3.29V. At input voltages less than 3.65, the VLDO regulator can be on dropout. The recommended capacitance for VLDO is 1μF of ceramic type. The VLDO can be loaded up to a maximum of 5mA.

Note: The VLDO output is not protected against short circuit conditions.
During power up, the user is recommended to wait at least 2.8ms (tStart_up_delay) after VIN > UVLORISE. This is to make sure all internal time constants are surpassed, otherwise the reference can be out of the ± 1% accuracy.

Each device generates an internal 1.2V bandgap reference that is used throughout the various internal control logic blocks. This is the voltage present on the REFCAP pin during steady state operation. This voltage is divided down to produce the reference for the comparator inputs at:

  1. SENSEx = 599.7mV (typical)
  2. SR_UVLO = 602mV (typical) during a rising voltage and 489mV during a falling voltage.
  3. WDI = 602mV (typical) during a rising voltage and 498mV during a falling voltage.
  4. MODE = 600mV (typical)during a rising voltage and 498mV during a falling voltage.
The VTH_SENSEx reference is measured at the RESETx outputs to account for offsets in the error amplifier and maintain regulation within ±1% across voltage, temperature, and radiation TID (up to 100krad in silicon). This tight reference tolerance allows the user to monitor voltage rails with high accuracy.

A 470nF capacitor to GND is required at the REFCAP pin for proper electrical operation as well as to provide robust SET performance of the device.