The SR_UVLO (system reset and undervoltage lockout) input pin allows for an external controller to propagate an external fault by asserting (or force low) all outputs at once. When SR_UVLO is low (< V_{TH_SR_UVLO_FALLING}) the device enters in shutdown mode and all outputs are forced logical low. As the SR_UVLO is the input to an accurate (± 3.17%) comparator with a rising threshold voltage of V_{TH_SR_UVLO_RISING} = 602mV, the designer can use the pin to set a external undervoltage lock-out if desired (refer to Figure 8-4). A fixed hysteresis of 103mV is incorporated in the comparator.

Usually the designer knows the voltage at which desired to enable the TPS7H3024. With that information, the resistive divider values can be calculated using Equation 1. Usually the top resistor is fixed to a 10kΩ value, but other values can be used. Using a larger value resistor minimizes power dissipation but can allow noise to couple into the outputs signal due a "weaker" pull-up.

where:

• V_{TH_SR_UVLO_RISING} is the internal reference during a rising voltage on SR_UVLO (602mV typically).
  • Rather than use the typical value the designer can use the centered to minimize the error across voltage, temperature and radiation as shown below:
    Equation 2. $\frac{{\mathrm{V}}_{\mathrm{T}\mathrm{H}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}\_\mathrm{R}\mathrm{I}\mathrm{S}\mathrm{I}\mathrm{N}\mathrm{G}\left(\mathrm{M}\mathrm{I}\mathrm{N}\right)+}{\mathrm{V}}_{\mathrm{T}\mathrm{H}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}\_\mathrm{R}\mathrm{I}\mathrm{S}\mathrm{I}\mathrm{N}\mathrm{G}\left(\mathrm{M}\mathrm{A}\mathrm{X}\right)}}{2}=\frac{0.580\mathrm{V}+\mathrm{ }0.618\mathrm{ }\mathrm{V}}{2}\mathrm{ }=\mathrm{ }0.599\mathrm{V}\mathrm{ }$
• V_{IN_UVLO_DESIRED} is the desired external voltage to enable the device during a rising voltage on V_IN.
• R_{TOP_SR_UVLO} is the selected top resistor for the divider.

Once the designer knows the actual (real) resistive divider values, Equation 3 and Equation 4 can be used to calculate the nominal rising and falling external undervoltage lockout as:

In Equation 4 the designer can use the centered across temperature, voltage and radiation (TID) as:

During startup the device needs to have a stable input voltage (UVLO_RISE ≤ V_IN ≤ 14) for at least 2.8ms (t_{START_UP_DELAY}). This is to make sure all internal time constants have been passed. This also makes sure that the V_{TH_SENSEx} reference is settled and the accuracy is within specification (1%). When V_IN is a fast rising voltage, an external delay capacitance can be add to the resistive divider to enable the device after the t_{START_UP_DELAY} have been exceed as shown in Figure 8-4. To select the capacitance (C_DELAY) for the SR_UVLO pin we can use Equation 6.

where:

• t_DELAY (s) is the desired delay time in seconds (at least 2.8ms after V_IN > UVLO_RISE).
• R_TH is the Thévenin equivalent resistance, which is the parallel between R_{TOP_SR_UVLO} and R_{BOTTOM_SR_UVLO} in ohms.
  • Equation 7. ${\mathrm{R}}_{\mathrm{T}\mathrm{H}} \left(\mathrm{\Omega }\right)=\frac{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}\mathrm{ }}\left(\mathrm{\Omega }\right)\times {\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}}\left(\mathrm{\Omega }\right)}{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}\mathrm{ }}\left(\mathrm{\Omega }\right)+{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}}\left(\mathrm{\Omega }\right)}$
• V_TH is the Thévenin equivalent voltage, which is the voltage at V_{SR_UVLO} during steady state operation in volts.
  • Equation 8. ${\mathrm{V}}_{\mathrm{T}\mathrm{H}} \left(\mathrm{V}\right)=\left(\frac{{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}}\left(\mathrm{\Omega }\right)}{{\mathrm{R}}_{\mathrm{T}\mathrm{O}\mathrm{P}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}\mathrm{ }}\left(\mathrm{\Omega }\right)+{\mathrm{R}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}\_\mathrm{S}\mathrm{R}\_\stackrel{\_\_\_\_\_\_}{\mathrm{U}\mathrm{V}\mathrm{L}\mathrm{O}}}\left(\mathrm{\Omega }\right)}\right)\times \mathrm{ }{\mathrm{V}}_{\mathrm{I}\mathrm{N}}\left(V\right)$
• V(t) is the voltage at SR_UVLO (V_{SR_UVLO}) which starts the sequence up. In this case 0.602V.
  • We can use the centered value across temperature and voltage as specified on Equation 2.