SNVSCS6 March   2026 TPS7H1301-SP

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable
      2. 9.3.2  Charge Pump
        1. 9.3.2.1 Charge Pump Operation
        2. 9.3.2.2 Foldback Switching
      3. 9.3.3  Startup
      4. 9.3.4  Power Good
      5. 9.3.5  Output Voltage
      6. 9.3.6  Dropout
      7. 9.3.7  Output Voltage Accuracy
      8. 9.3.8  Output Noise
      9. 9.3.9  Power Supply Rejection Ratio
      10. 9.3.10 Stability
        1. 9.3.10.1 Stability of the TPS7H1301
        2. 9.3.10.2 Stability of the TPS7H1302
      11. 9.3.11 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable Disable
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Capacitor Selection
          1. 10.2.2.1.1 Input Capacitor (CIN) Selection
          2. 10.2.2.1.2 CFLY
          3. 10.2.2.1.3 CPOUT Capacitor
          4. 10.2.2.1.4 Bypass Capacitors
          5. 10.2.2.1.5 Output Capacitor
        2. 10.2.2.2 Charge Pump Output Resistance
        3. 10.2.2.3 Output Noise
        4. 10.2.2.4 PSRR Design Implications
        5. 10.2.2.5 Stability Design Considerations
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     69

9.3.9 Power Supply Rejection Ratio

The Power Supply Rejection Ratio (PSRR) of the TPS7H1301 and TPS7H1302 quantifies the ability of the device to attenuate input noise present at VCPOUT from appearing at the regulated output VOUT. PSRR is mathematically defined as the ratio of input voltage variation to the corresponding output voltage variation, typically expressed in decibels (dB). PSRR is mathematically defined in Equation 7.

Equation 7. P S R R   = 20 × l o g 10 (   V C P O U T ( A C ) V O U T ( A C ) )

Noise Source Characteristics

The primary source of input noise in these devices originates from the switching ripple generated by the internal inverting charge pump circuit. This switching noise manifests at the fundamental switching frequency and associated switching frequency harmonics:

  • TPS7H1301: 500kHz (typ) switching frequency
  • TPS7H1302: 1000kHz (typ) switching frequency

Impact of External Compensation (TPS7H1301 only)

When an external compensation network is implemented, the resulting reduction in control loop bandwidth directly affects PSRR performance. A narrower loop bandwidth limits the ability of the regulator to reject input disturbances, particularly at higher frequencies, leading to diminished overall PSRR performance compared to the standard configuration.