SNVSCT9A October   2024  – February 2025 LM251772

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Reference System
        1. 8.3.3.1 VIO LDO and nRST-PIN
      4. 8.3.4  Supply Voltage Selection – VSMART Switch and Selection Logic
      5. 8.3.5  Enable and Undervoltage Lockout
        1. 8.3.5.1 UVLO
      6. 8.3.6  Internal VCC Regulators
        1. 8.3.6.1 VCC1 Regulator
        2. 8.3.6.2 VCC2 Regulator
      7. 8.3.7  Error Amplifier and Control
        1. 8.3.7.1 Output Voltage Regulation
        2. 8.3.7.2 Output Voltage Feedback
        3. 8.3.7.3 Voltage Regulation Loop
        4. 8.3.7.4 Dynamic Voltage Scaling
      8. 8.3.8  Output Voltage Discharge
      9. 8.3.9  Peak Current Sensor
      10. 8.3.10 Short Circuit - Hiccup Protection
      11. 8.3.11 Current Monitor/Limiter
        1. 8.3.11.1 Overview
        2. 8.3.11.2 Output Current Limitation
        3. 8.3.11.3 Output Current Monitor
      12. 8.3.12 Oscillator Frequency Selection
      13. 8.3.13 Frequency Synchronization
      14. 8.3.14 Output Voltage Tracking
        1. 8.3.14.1 Analog Voltage Tracking
        2. 8.3.14.2 Digital Voltage Tracking
      15. 8.3.15 Slope Compensation
      16. 8.3.16 Configurable Soft Start
      17. 8.3.17 Drive Pin
      18. 8.3.18 Dual Random Spread Spectrum – DRSS
      19. 8.3.19 Gate Driver
      20. 8.3.20 Cable Drop Compensation (CDC)
      21. 8.3.21 CFG-pin and R2D Interface
      22. 8.3.22 Advanced Monitoring Features
        1. 8.3.22.1  Overview
        2. 8.3.22.2  BUSY
        3. 8.3.22.3  OFF
        4. 8.3.22.4  VOUT
        5. 8.3.22.5  IOUT
        6. 8.3.22.6  INPUT
        7. 8.3.22.7  TEMPERATURE
        8. 8.3.22.8  CML
        9. 8.3.22.9  OTHER
        10. 8.3.22.10 ILIM_OP
        11. 8.3.22.11 nFLT/nINT Pin Output
        12. 8.3.22.12 Status Byte
      23. 8.3.23 Protection Features
        1. 8.3.23.1  Thermal Shutdown (TSD)
        2. 8.3.23.2  Over Current Protection
        3. 8.3.23.3  Output Over Voltage Protection 1 (OVP1)
        4. 8.3.23.4  Output Over Voltage Protection 2 (OVP2)
        5. 8.3.23.5  Input Voltage Protection (IVP)
        6. 8.3.23.6  Input Voltage Regulation (IVR)
        7. 8.3.23.7  Power Good
        8. 8.3.23.8  Boot-Strap Under Voltage Protection
        9. 8.3.23.9  Boot-strap Over Voltage Clamp
        10. 8.3.23.10 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ from a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. 9 LM251772 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 MOSFETs QH1 and QL1
        11. 10.2.2.11 MOSFETs QH2 and QL2
        12. 10.2.2.12 Loop Compensation
        13. 10.2.2.13 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 Wireless Charging Supply
    4. 10.4 USB-PD Source with Power Path
    5. 10.5 Parallel (Multiphase) Operation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

LM251772 RHA Package 40-Pin QFN Top ViewFigure 5-1 RHA Package 40-Pin QFN Top View
Table 5-1 Pin Functions
PINI/O(1)DESCRIPTION
NAMENO.
VCC11OAuxiliary 5V regulator output. Place a capacitor close to the pin for good decoupling. If the output is disabled by the logic it can be tied to GND with a resistor or pulled to VCC2. Do not leave the pin floating.
SS/ATRK2I/OSoft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.

Analog output voltage tracking pin. The VOUT regulation target can be programmed by connecting the pin to variable voltage reference (for example, through a digital to analog converter). The internal circuit selects the lowest voltage between the pin voltage and the internal voltage reference.

SYNC3ISynchronization clock input/output. The internal oscillator can be synchronized to an external clock during operation. Do not leave this pin floating. If this function is not used, connect the pin to VCC2 or GND.

The SYNC pin can be configured as clock synchronization output signal. The clock phase can be selected to 0° and 180° to directly operate two devices in a parallel (dual phase) operation.

DTRK4IDigital PWM input pin for the dynamic output voltage tracking. Do not leave this pin floating. If this function is not used, connect the pin to VCC or GND.
SDA5I/OI2C interface serial data line. Connect an external a pull-up resistor
SCL6II2C interface serial clock line. Connect an external a pull-up resistor
MODE7IDigital input to select device operation mode. If the pin is pulled low, power save mode (PSM) is enabled. If the pin is pulled high, the forced PWM or CCM operation is enabled. The configuration can be changed dynamically during operation. Do not leave this pin floating.
CFG28I/ODevice configuration pin. Connect a resistor between the CFG2 pin and GND to select the device operation according the Section 8.3.21
ADDR(CFG1)9I

Address selection. Pull to GND for I2C target address LSB = 0. Pull to VCC2 for I2C target address LSB = 1

CDC10Cable drop compensation or current monitor output pin. Connect a resistor between the CDC pin and AGND to select the gain for the cable drop compensation.

Per default this pin provides a current monitoring signal of the sensed voltage between the ISNSP and ISNSN pins

In case the current monitor is disabled connect CDC to ground

nFLT/nINT11OOpen-drain output pin for fault indication or power good. This pin can be configured as interrupt pin. In case of a STATUS register change the pin toggles low for 256μs.
RT12I/OSwitching frequency programming pin. An external resistor is connected to the RT pin and AGND to set the switching frequency
COMP13OOutput of the error amplifier. An external RC network needs to be connected between COMP and AGND to stabilize/compensate the regulator voltage loop.
FB/SEL_intFB14IFeedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin. Connect the FB pin to VCC2 to operate at a fixed output voltage default setting of the device.

To select the internal feedback connect the pin to VCC2 before the device start-up

AGND15

Connect to AGND

ILIMCOMP16Compensation pin for average current limit loop. Connect an capacitor or a type 2 R-C network if the current limit is set by the internal DAC.

If the internal DAC is disabled the pin sets the current limit threshold for the average current limit. Connect a resistor to AGND. A parallel filter of capacitor is recommended depending on the application requirements

Connect the ILIMCOMP pin to VCC2 to disable the block and reduce the quiescent current

AGND17GAnalog Ground
VOUT18IOutput voltage sense input. Connect to the power stage output rail.
ISNSN19INegative sense input of the output or input average current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be located either on the input side or on the output side of the power stage.

In case the optional current sensor is disabled connect ISNSN and ISNSP together to AGND

ISNSP20IPositive sense input of the output or input current sense amplifier. An optional current sense resistor connected between ISNSN and ISNSP can be placed either on the input side or on the output side of the power stage.

In case the optional current sensor is disabled connect ISNSP to ground

CSB21IInductor peak current sense negative input. Connect CSB to the negative side of the external current sense resistor using a Kelvin connection.
CSA22IInductor peak current sense positive input. Connect CSA to the positive side of the external current sense resistor using a Kelvin connection.
SW123PInductor switch node for the buck half-bridge
HO124OHigh-side gate driver output for the buck half-bridge
HB125PBootstrap supply pin for buck half-bridge. An external capacitor is required between the HB1 pin and the SW1 pin, to provide bias to the high-side MOSFET gate driver.

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling

NC26ONot Connected
LO127OLow-side gate driver output for the buck half-bridge
PGND 28GPower Ground
VCC229OInternal linear bias regulator output. Connect a ceramic decoupling capacitor from VCC to PGND. This rail supplies the internal logic and the gate driver.

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling.

LO230OLow-side gate driver output for the boost half-bridge
HB231PBootstrap supply pin for boost half-bridge. An external capacitor is required between the HB2 pin and the SW2 pin, to provide bias to the high-side MOSFET gate driver

Place the external capacitor close to the pin without any resistance between the pin and capacitor for good decoupling

HO232OHigh-side gate driver output for the boost half-bridge
SW233PInductor switch node for the boost half-bridge
NC34ONot Connected
DRV135External FET drive pin. This pin features a high-voltage push pull stage, a open drain output or a charge pump driver stage according to the selected configuration.

In case the optional DRV pin is not used you can leave DRV open.

VIN36IThe input supply and sense input of the device. Connect VIN to the supply voltage of the power stage.
EN/UVLO37IEnable pin. Digital input pin to enable the converter switching.

The input features a precise analog comparator and a hysteresis to monitor the input voltage. Connect a resistor divider from the input voltage to maintain the under voltage lookout(UVLO) feature.

nRST38IDigital input pin to enable the device internal logic, interface operation and the VCC1 regulator if selected.
NC39ONot Connected
BIAS40Optional input to the VCC2 bias regulator. Powering VCC2 from an external supply instead of VIN can reduce power loss at high VIN.
GNDPADGThermal pad
  1. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.