The NRST pin (pin 20) is used to reset the device logic/enable device internal logic and IO interface. When the NRST voltage is below threshold level all power switches, references, controls, and bias circuitry of the LP87524B/J/P-Q1 device are turned off. When NRST is set to high level (and VANA is above UVLO level) this initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I²C host must allow at least 1.2 ms before writing or reading data to the LP87524B/J/P-Q1. Device enters STANDBY-mode after internal startup sequence. The host can change the default register setting by I²C if needed. The regulator(s) can be enabled/disabled by ENx pin(s) or by I²C interface.